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參數(shù)資料
| 型號： | CYM1464PD-55C |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512Kx8 Static RAM Module |
| 中文描述： | 512K X 8 MULTI DEVICE SRAM MODULE, 55 ns, DMA32 |
| 封裝： | MODULE, DIP-32 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 200K |
| 代理商： | CYM1464PD-55C |
CYM1464
Document #: 38-05272 Rev. **
Page 3 of 8
Switching Characteristics
Over the Operating Range
[3]
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
WRITE CYCLE
[5]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Description
1464-20
Min.
1464-22
Min.
1464-25
Min.
1464-30
Min.
Unit
Max.
Max.
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
CS HIGH to High Z
[4]
20
22
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
22
25
30
5
5
5
5
20
13
22
13
25
15
30
15
0
0
5
0
0
0
5
0
0
0
5
0
0
0
10
10
10
10
10
0
15
15
15
20
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[4]
20
15
15
3
5
15
12
2
0
22
17
15
3
5
15
12
2
0
25
20
20
3
5
15
15
2
0
30
25
25
3
5
20
15
2
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
15
15
Switching Characteristics
Over the Operating Range
[3]
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
Notes:
3.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
4.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
5.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Description
1464-35
Min.
1464-45
Min.
1464-55
Min.
Unit
Max.
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
CS HIGH to High Z
[4]
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
45
55
5
5
5
35
20
45
25
55
30
0
0
10
0
0
0
0
0
15
15
15
10
0
10
0
20
20
20
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