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參數(shù)資料
| 型號： | CYM1471 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1024K x 8 SRAM Module(1024K x 8 靜態(tài)RAM模塊) |
| 中文描述： | 1024K × 8的SRAM模塊（1024K × 8靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 248K |
| 代理商： | CYM1471 |
CYM1471
CYM1481
:
3
AC Test Loads and Waveforms
1471-3
1471-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 10 ns
< 10 ns
OUTPUT
R1 2530
R2
2830
1340
Equivalent to:
THé VENIN EQUIVALENT
2.64V
100 pF
R1 2530
R2
2830
1471-5
Switching Characteristics
Over the Operating Range
[2]
1471-70
1481-70
Min
1471–85
1481–85
Min.
1471–100
1481–100
Min.
1471–120
1481–120
Min.
Parameter
Description
Max
Max.
Max.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
AMS
t
DOE
t
LZOE
t
HZOE
t
LZMS
t
HZMS
WRITE CYCLE
[5]
t
WC
t
SMS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
2.
Test conditions assume signal transition time of 10
μ
s or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of 1 TTL load, and
100-pF load capacitance.
3.
t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
4.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed and not 100% tested.
5.
The internal write time of the memory is defined by the overlap of MS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Read Cycle Time
70
85
100
120
ns
Address to Data Valid
70
85
100
120
ns
Data Hold from Address Change
5
10
10
10
ns
MS LOW to Data Valid
70
85
100
120
ns
OE LOW to Data Valid
40
45
50
60
ns
OE LOW to Low Z
OE HIGH to High Z
[3]
MS LOW to Low Z
[4]
MS HIGH to High Z
[3, 4]
5
5
5
5
ns
30
30
35
45
ns
5
10
10
10
ns
30
30
35
45
ns
Write Cycle Time
70
85
100
120
ns
MS LOW to Write End
65
75
90
100
ns
Address Set-Up to Write End
65
75
90
100
ns
Address Hold from Write End
5
7
7
7
ns
Address Set-Up to Write Start
0
5
5
5
ns
WE Pulse Width
65
65
75
85
ns
Data Set-Up to Write End
30
35
40
45
ns
Data Hold from Write End
WE LOW to High Z
[3]
0
5
5
5
ns
30
30
35
40
ns
WE HIGH to Low Z
5
5
5
5
ns
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