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參數(shù)資料
| 型號(hào)： | CYM1841C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 32 Static RAM Module(256K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 256K × 32靜態(tài)RAM模塊（256K × 32靜態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 274K |
| 代理商： | CYM1841C |
CYM1841A
CYM1841C
4
Switching Characteristics
Over the Operating Range
[4]
1841C-12
Min.
1841C-15
Min.
1841A-20
1841C-20
Min.
1841A-25
1841C-25
Min.
Parameter
Description
Max.
Max.
Max.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[7]
Read Cycle Time
12
15
20
25
ns
Address to Data Valid
12
15
20
25
ns
Output Hold from Address Change
3
3
3
3
ns
CS LOW to Data Valid
12
15
20
25
ns
OE LOW to Data Valid
7
8
13
15
ns
OE LOW to Low Z
0
0
0
0
ns
OE HIGH to High Z
CS LOW to Low Z
[5]
CS HIGH to High Z
[5, 6]
7
8
15
15
ns
3
3
10
10
ns
7
8
20
20
ns
CS HIGH to Power-Down
12
15
20
25
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Shaded area contains preliminary information.
Notes:
4.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
5.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed by design and not 100% tested.
6.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
7.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Write Cycle Time
12
15
20
25
ns
CS LOW to Write End
9
10
15
20
ns
Address Set-Up to Write End
9
10
18
20
ns
Address Hold from Write End
0
0
0
0
ns
Address Set-Up to Write Start
2
2
2
2
ns
WE Pulse Width
10
13
15
20
ns
Data Set-Up to Write End
7
8
13
15
ns
Data Hold from Write End
1
1
2
2
ns
WE HIGH to Low Z
WE LOW to High Z
[6]
0
0
0
0
ns
0
5
0
7
0
15
0
15
ns
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