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參數(shù)資料
| 型號： | CYM1946 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512K x 32 Static RAM Module(512K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 512k × 32的靜態(tài)RAM模塊（512k × 32的靜態(tài)內存模塊） |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 158K |
| 代理商： | CYM1946 |
CYM1946
3
AC Test Loads and Waveforms
1946–3
1946–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 5 ns
< 5 ns
OUTPUT
R1 481
R1 481
R2
255
R2
255
167
Equivalent to:
THé VENIN
EQUIVALENT
1.73V
Switching Characteristics
Over the Operating Range
[3]
1946-35
Min.
1946-45
Min.
1946-55
Min.
Parameter
Description
Max.
Max.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[6]
Read Cycle Time
35
45
55
ns
Address to Data Valid
35
45
55
ns
Data Hold from Address Change
5
5
5
ns
CS LOW to Data Valid
35
45
55
ns
OE LOW to Data Valid
15
17
22
ns
OE LOW to Low Z
0
0
0
ns
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
12
17
22
ns
10
10
10
ns
17
22
27
ns
CS HIGH to Power-Down
35
45
55
ns
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
3.
Write Cycle Time
35
45
55
ns
CS LOW to Write End
30
40
50
ns
Address Set-Up to Write End
30
40
50
ns
Address Hold from Write End
5
5
5
ns
Address Set-Up to Write Start
2
2
2
ns
WE Pulse Width
30
35
45
ns
Data Set-Up to Write End
20
25
35
ns
Data Hold from Write End
7
7
7
ns
WE HIGH to Low Z
WE LOW to High Z
[5]
5
5
5
ns
15
15
15
ns
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed and not 100% tested.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
4.
5.
6.
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