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參數(shù)資料
| 型號： | DJLXT972MTAA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 81/92頁 |
| 文件大?。?/td> | 666K |
| 代理商： | DJLXT972MTAA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
81
Table 47
lists auto-negotiation expansion bits.
Table 47. Auto-Negotiation Expansion - Address 6, Hex 6
Bit
Name
Description
Type
1
Default
6.15:6
Reserved
Ignore when read.
RO
0
6.5
Base Page
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with the
auto-negotiation state diagram, allowing detection of
interrupted links. This bit is used only if Register bit
16.1 (that is, Alternate NP feature) is set.
0 = Base page = False (base page not received)
1 = Base page = True (base page received)
RO/LH
0
6.4
Parallel
Detection Fault
0 = Parallel detection fault has not occurred.
1 = Parallel detection fault has occurred.
RO/LH
0
6.3
Link Partner
Next Page Able
0 = Link partner is not next page able.
1 = Link partner is next page able.
RO
0
6.2
Next Page Able
0 = Local device is not next page able.
1 = Local device is next page able.
RO
1
6.1
Page Received
This bit is cleared on Read. If Register bit 16.1 is set,
the Page Received bit is also cleared when either
mr_page_rx = false or transmit_disable = true.
1 = Indicates a new page is received and the received
code word is loaded into Register 5 (Base Pages)
or Register 8 (Next Pages) as specified in Clause
28 of IEEE 802.3.
RO/LH
0
6.0
Link Partner A/N
Able
0 = Link partner is not auto-negotiation able.
1 = Link partner is auto-negotiation able.
RO
0
1. RO = Read Only LH = Latching High
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| DJLXT972MTCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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