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Pin Connections
MOTOROLA WIRELESS
RF PRODUCT DEVICE DATA
MC145170-2
4–17
LD
Lock Detector Output (Pin 11)
This output is essentially at a high level with narrow low-going pulses when the loop is locked (f
R
and f
V
of the same phase and frequency). The output pulses low when f
V
and f
R
are out of phase or different
frequencies (see Figure 19).
This output can be enabled and disabled via the C register (patented). Upon power up, on-chip
initialization circuitry disables LD to a static low logic level to prevent a false “l(fā)ock” signal. If unused, LD
should be disabled and left open.
3.5 Power Supply
V
DD
Most Positive Supply Potential (Pin 16)
This pin may range from 2.7 to 5.5 V with respect to V
SS
.
For optimum performance, V
DD
should be bypassed to V
SS
using low-inductance capacitor(s) mounted
very close to the device. Lead lengths on the capacitor(s) should be minimized. (The very fast switching
speed of the device causes current spikes on the power leads.)
V
SS
Most Negative Supply Potential (Pin 12)
This pin is usually ground. For measurement purposes, the V
SS
pin is tied to a ground plane.
Figure 15. Reset Sequence
ENB
CLK
D
in
Power Up
1
2
3
4 or More Clocks
5
1
2
3
4
Don't Cares
Don't Cares
One
Zeroes
Zero
NOTE:
This initialization sequence is usually not necessary because the on-chip power-on reset circuit performs the
initialization function. However, this initialization sequence must be used immediately after power up if control of the
CLK pin is not possible. That is, if CLK (Pin 7) toggles or floats upon power up, use the above sequence to reset the
device. Also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is
reduced to below 2.7 V, but not down to at least 1 V (for example, the supply drops down to 2 V). This is necessary
because the on-chip power-on reset is only activated when the supply ramps up from a voltage below
approximately 1.0 V.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.