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參數(shù)資料
| 型號： | DP8390CV |
| 英文描述： | LAN Node Controller |
| 中文描述： | 網(wǎng)絡節(jié)點控制器 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 240K |
| 代理商： | DP8390CV |
60 Register Description (Continued)
616 PORT ATTRIBUTE STATUS REGISTER 1
The Port Attribute Status Registers 1 and 2 are located in the Port Attribute memory map of each port Port Attribute Registers 1
and 2 are used to indicate if any attributes have changed since the last CPU access to a particular port These registers
therefore provide a status indication of any attribute changes
The CPU needs to ensure that the port Attributes are cleared after a CPU read to these two registers This will guarantee that
the CPU has taken a snap-shot of the Port Attributes correctly The Management block of the DP83957 automatically updates
the attributes on a port-per-packet basis
Reset State
Undefined (SRAM)
Bit
Bit Name
Access
Bit Description
D7
LEVNT
ReadWrite
This status bit indicates whether a port experienced a Late Event
D6
COL
ReadWrite
This status bit indicates whether a port experienced a Collision
D5
RUNT
ReadWrite
This status bit indicates whether a port experienced a Runt
D4
SEVNT
ReadWrite
This status bit indicates whether a port experienced a Short Event
D3
FTL
ReadWrite
This status bit indicates whether a port experienced a Frame Too Long condition
D2
AERR
ReadWrite
This status bit indicates whether a port experienced an Alignment Error
D1
FCSERR
ReadWrite
This status bit indicates whether a port experienced a Frame Check Sequence Error on a packet
D0
RFO
ReadWrite
This status bit indicates whether a port experienced a Readable Frame or a frame with Readable
Octets
617 PORT ATTRIBUTE STATUS REGISTER 2
Port Attribute Status Register 2 is an extension to the Port Attribute Status Register 1 for any port
Reset State
Undefined (SRAM)
Bit
Bit Name
Access
Bit Description
D7 – D3
RES
Reserved
D2
SAC
ReadWrite
This status bit indicates whether a port experienced a change of Source Address from the
address stored in the aLastSourceAddress attribute
D1
DRM
ReadWrite
This status bit indicates whether the port experienced a Data Rate Mismatch
D0
VLE
ReadWrite
This status bit indicates whether the port experienced a Very Long Event
19
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DP8390CV-1 | LAN Node Controller |
| DP8390N | LAN Node Controller |
| DP83910N | Communications Interface |
| DP83932CVF20 | LAN Node Controller |
| DP83932CVF25 | LAN Node Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DP8390CV-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| DP8390D | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NIC Network Interface Controller |
| DP8390D/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| DP8390D/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| DP8390DN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NIC Network Interface Controller |
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