參數(shù)資料
型號(hào)： DP83910N
英文描述： Communications Interface
中文描述： 通信接口
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 240K
代理商： DP83910N
30 Pin Description
31 CPU INTERFACE
The CPU interface is a generic 8-bit multiplexed AddressData bus The asynchronous interface requires minimum glue logic
Signal Name
Type
Active
Description
CS
OC
Low
CHIP SELECT
The Chip Select is generated by the system to select the DP83957 registers
Chip Select must remain valid for the entire cycle
RD
OC
Low
READ
Read Data Strobe The system asserts this pin low to read the DP83957 registers
WR
OC
Low
WRITE
Write Data Strobe The system asserts this pin low to write to the DP83957 registers
ALE
IC
High
ALE
Address Latch Enable The system needs to drive this to inform the DP83957 that there
is a valid address on the AddressData bus
INT
OZC
Low
INTERRUPT
Indicates that an interrupt (if enabled) is pending from one of the sources set in
the Interrupt Status Register
AD 70
OIZC
ADDRESSDATA BUS
8-bit multiplexed CPU addressdata bus
32 SRAM INTERFACE
The SRAM interface is used to connect the DP83957 to an external SRAM The DP83957 supports either a 1kx8or2kx 8-bit
SRAM The SRAM interface can support SRAM access times of 25 ns and 45 ns
Signal Name
Type
Active
Description
SRD 70
OIZ
SRAM DATA BUS
This data bus should be connected directly to the external SRAM
SRA 130
OC
SRAM ADDRESS BUS
This address bus should be connected directly to a 1kx8or2kx8
SRAM Address inputs
SRW
IC
SRAM READ-WRITE
A high level signal indicates a Read and a low level signals indicates a
Write cycle
SROE
IC
Low
SRAM OUTPUT ENABLE
This should be connected directly to the external SRAM output
enable
4
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