參數(shù)資料
型號: DP83910N
英文描述: Communications Interface
中文描述: 通信接口
文件頁數(shù): 20/24頁
文件大小: 240K
代理商: DP83910N
30 Pin Description (Continued)
33 MANAGEMENT BUS INTERFACE
The Management Bus Interface provides the input to the DP83957 from the DP83950 or the DP83952 The Management Bus
connects directly to the DP83950 or DP83952 or through buffers depending on the repeater design (refer to the DP83950 data
sheet)
The Management Bus is a NRZ bus that provides the necessary information to the DP83957 so that it can assemble port
attributes on a per-port per-packet basis
Signal Name
Type
Active
Description
MRXC
IC
MANAGEMENT RECEIVE CLOCK
When asserted this signal provides a clock signal for
the MRXD serial data stream The MRXD signal is changed on the falling edge of this clock
MRXD
IC
MANAGEMENT RECEIVE DATA
When asserted this signal provides a serial data stream
in NRZ format The data stream is made up of the packet data and DP839502 status
information
MCRS
IC
High or Low
MANAGEMENT CARRIER SENSE
When asserted this signal provides an activity framing
enable for the serial output data stream (MRXD)
(Selectable)
34 MISCELLANEOUS PINS
Signal Name
Type
Active
Description
CLK
IC
CLOCK
40 MHz clock for the internal state machines This clock does not influence the
asynchronous CPU Interface This clock can be obtained directly from the DP839502
RESET
IC
Low
RESET
The DP83957 is reset when this signal is asserted low Asserting this signal will cause all
the state machines and registers to enter their reset state
RES
RESERVED
Leave as No Connect
VCC
I
VCC a5V supply
GND
I
GND
Ground return
35 PIN TYPE DESIGNATION
Type
Description
I
Input Buffer
O
Output
Z
High Impedance State
IOZ
Bi-directional buffer with high impedance capability
C
CMOS input or output
5
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DP83910V 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Interface
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