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Table of Contents
10 SYSTEM DIAGRAM
20 PIN CONNECTION DIAGRAM
30 PIN DESCRIPTION
31 CPU Interface
32 SRAM Interface
33 Management Bus Interface
34 Miscellaneous Pins
35 Pin Type Designation
40 BLOCK DIAGRAM
50 FUNCTIONAL DESCRIPTION
51 SRAM Interface
511 SRAM Configuration
512 SRAM Read Operation
513 SRAM Write Operation
514 SRAM Memory Map
515 SRAM Address Format
52 Management Interface
521 Management Configuration
522 Management Bus Interface
523 Management Bus Processing
524 Port Attributes
525 Port Attribute Status
526 Port Attribute Overflow
53 CPU Interface
531 Register Read Operation
532 Register Write Operation
533 Interrupts
54 Registers
60 REGISTER DESCRIPTIONS
61 Register Map
62 Configuration Register 1
63 Configuration Register 2
64 Configuration Register 3
65 Interrupt Mask Register
66 Interrupt Status Register
67 Read Data Transfer Registers 1 – 6
68 Access Register 1
69 Access Register 2
610 Write Data Byte Register
611 DP83950 ID 1 Register
612 DP83950 ID 2 Register
613 Overflow Status 1 Register
614 Overflow Status 2 Register
615 DP83957 Revision Register
616 Port Attribute Status Register 1
617 Port Attribute Status Register 2
70 DC SPECIFICATIONS
80 AC SPECIFICATIONS
81 CPU Read Timing
82 CPU Write Timing
83 Management Bus Interface Timing
84 Reset Timing
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