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參數(shù)資料
| 型號： | DS1073 |
| 英文描述： | EconOscillator/Divider |
| 中文描述： | EconOscillator /分頻器 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 260K |
| 代理商： | DS1073 |
DS1073
6 of 18
OPERATION OF OUTPUT ENABLE
Since the output enable, internal master oscillator and/or external master oscillator are likely all
asynchronous there is the possibility of timing difficulties in the application. To minimize these
difficulties the DS1073 features an “enabling sequencer” to produce predictable results when the device is
enabled and disabled. In particular the output gating is configured so that truncated output pulses can
never be produced.
ENABLE TIMING
The output enable function is produced by sampling the OE input with the output from the prescaler mux
(MCLK) and gating this with the output from the programmable divider. The exact behavior of the
device is therefore dependent on the setup time (t
SU
) from a transition on the OE input to the rising edge
of MCLK. If the actual setup time is less than t
SUEM,
then one more complete cycle of MCLK will be
required to complete the enable or disable operation (see diagrams). This is unlikely to be of any
consequence in most applications, and then only if the value for N is small. In general, the output will
make its first positive transition between approximately one and two clock periods of MCLK after the
rising edge of OE.
Figure 4
DISABLE TIMING
If OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If
OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE
and the rising edge of MCLK. If t
SU
< t
SUEM
the result will be one additional pulse appearing on the
output before disabling occurs.
If the device is in divide-by-one mode, the disabling occurs slightly differently. In this case if t
SU
> t
SUEM
one additional output pulse will appear, if t
SU
< t
SUEM
then two additional output pulses will appear.
The following diagrams illustrate the timing in each of these cases.
Figure 5
t
M
= PERIOD OF MCLK
t
d
= PROP DELAY FROM MCLK TO OUT
MAX VALUE OF t
en
= t
SUEM
+ 2 t
M
+ t
d
MIN VALUE OF ten = t
SUEM
+ t
M
+ t
d
t
M
= PERIOD OF MCLK
t
d
= PROP DELAY FROM MCLK TO OUT
t
OUTH
= WIDTH OF OUTPUT PULSE
MAX VALUE OF t
dis
= t
SUEM
+ t
d
+ t
OUTH
MIN VALUE OF t
dis
= 0
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS10730-030 | 功能描述:可編程振蕩器 RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| DS10730-030 DIE | 制造商:Maxim Integrated Products 功能描述: |
| DS1073M-100 | 功能描述:可編程振蕩器 RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| DS1073M-60 | 功能描述:可編程振蕩器 RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| DS1073M-66 | 功能描述:可編程振蕩器 RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
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