參數資料
型號: DS1086
英文描述: 10/100/1000 Base-T Ethernet LAN Switch
中文描述: 擴頻EconOscillator
文件頁數: 9/14頁
文件大?。?/td> 229K
代理商: DS1086
D
DS1086 Spread-Spectrum EconOscillator
_____________________________________________________________________
9
The output frequency is determined by the following
equation:
where:
min frequency of selected OFFSET range
is the
lowest frequency (shown in
Table
2 for the correspond-
ing offset).
DAC value
is the value of the DAC register (0 to 1023).
Prescaler
is the value of 2
x
where x = 0 to 8.
See the
Example Frequency Calculations
section for a
more in-depth look at using the registers.
________________Register Definitions
The DS1086 registers are used to determine the output
frequency and dither amount. A summary of the regis-
ters is shown in
Table
1. Using the default register set-
tings below, the default output frequency is 97.1MHz.
See the
Example Frequency Calculations
section for an
example on how to determine the register settings for a
desired output frequency.
PRESCALER Register
The PRESCALER register controls the prescaler (bits P3
to P0) and dither (bit J0). The prescaler divides the mas-
ter oscillator frequency by 2
x
where x can be from 0 to 8.
Any prescaler value entered that is greater than 8
decodes as 8. The dither applied to the output is con-
trolled with bit J0. When J0 is high, 2% peak dither is
selected. When J0 is low, 4% peak dither is selected.
DAC HIGH/DAC LOW Register
The 2-byte DAC register sets the frequency of the master
oscillator to a particular value within the current offset
range. Each step of the DAC changes the master oscilla-
tor frequency by 10kHz. The first byte is the MSB (DAC
HIGH) and the second byte is the LSB (DAC LOW).
OFFSET Register
The OFFSET register determines the range of frequencies
that can be obtained for a given DAC setting. The factory
default offset is copied into the RANGE register so the
user can access the default offset after making changes
to the OFFSET register. See
Table
2 for OFFSET ranges.
Correct operation of the device is not guaranteed out-
side the range 66MHz to 133MHz.
f
OUTPUT
MIN FREQUENCY OF SELECTED OFFSET RANGE
DAC VALUE
PRESCALER
kHz STEP SIZE
=
(
)
(
×
10
)
+
SDA
SCL
2-WIRE
INTERFACE
V
CC
DAC
OFFSET
EEPROM CONTROL
REGISTERS
PRESCALER
ADDR
RANGE
SPRD
PDN
OUT
OE
DAC
TRIANGLE WAVE
GENERATOR
VOLTAGE-CONTROLLED
OSCILLATOR
PRESCALER
BY 1, 2, 4...256
GND
MASTER
OSCILLATOR
OUTPUT
DITHER SIGNAL
DITHER
CONTROL
FREQUENCY
CONTROL VOLTAGE
DS1086
Figure 3. DS1086 Block Diagram
(1)
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相關代理商/技術參數
參數描述
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