Note 1: Typical values are at TA = +25°C, VCC
參數(shù)資料
型號(hào): DS1682S+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 9/14頁
文件大?。?/td> 0K
描述: IC TIMEKEEPER ALARM ELAPSE 8SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 耗用時(shí)間計(jì)數(shù)器
特點(diǎn): 警報(bào)器,EEPROM
存儲(chǔ)容量: 10B
時(shí)間格式: 二進(jìn)制
數(shù)據(jù)格式: 二進(jìn)制
接口: I²C,2 線串口
電源電壓: 2.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
Note 1: Typical values are at TA = +25°C, VCC = 4.0V.
Note 2: The elapsed time and event counters are backed by three EEPROM arrays, which are used sequentially, allowing up to 3 x
EE. The configuration register, alarm trip-point register, and user memory use a single array, limiting them to one EE.
Note 3: A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended. A typical value is
0.01μF. VCC must be maintained above VCC minimum, including transients, during EEPROM writes.
Note 4: VCC must be at or above 2.5V for tEW after the end of an event to ensure data transfer to the EEPROM.
Note 5: Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must be met. This is
automatically the case if the device does not stretch the tLOW. If such a device does stretch tLOW, it must output the next
data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
Note 10: CB—Total capacitance of one bus line in pF.
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
DS1682
Total-Elapsed-Time Recorder
with Alarm
www.maximintegrated.com
Maxim Integrated │ 4
Timing Diagram
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