參數(shù)資料
型號(hào): DS3154N
英文描述: Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
中文描述: 單/雙/三/四DS3/E3/STS-1柳斯
文件頁(yè)數(shù): 35/60頁(yè)
文件大?。?/td> 788K
代理商: DS3154N
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
35 of 60
12.3 JTAG Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO. A
rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update-
IR state. The falling edge of that same JTCLK latches the
data in the instruction shift register to the instruction
parallel output.
Table 12-A
shows the instructions supported by the DS315x and their respective operational binary
codes.
Table 12-A. JTAG Instruction Codes
INSTRUCTIONS
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
SELECTED REGISTER
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
INSTRUCTION CODES
010
111
000
011
100
001
SAMPLE/PRELOAD.
SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This
instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register
without interfering with the device’s normal operation by using the Capture-DR state. SAMPLE/PRELOAD also
allows the DS315x to shift data into the boundary scan register through JTDI using the Shift-DR state.
EXTEST.
EXTEST allows testing of the interconnections to the device. When the EXTEST instruction is latched in
the instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs
of the digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The
Capture-DR samples all digital inputs into the boundary scan register.
BYPASS.
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s
normal operation.
IDCODE.
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code is loaded into the identification register on the rising edge of
JTCLK, following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially
through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel
output.
HIGHZ.
All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI
and JTDO.
CLAMP.
All digital output pins output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
Table 12-B. JTAG ID Code
PART
DS3154
DS3153
DS3152
DS3151
REVISION
Consult factory
Consult factory
Consult factory
Consult factory
DEVICE CODE
0000000000110011
0000000000110010
0000000000110000
0000000000100000
MANUFACTURER CODE
00010100001
00010100001
00010100001
00010100001
REQUIRED
1
1
1
1
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