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參數(shù)資料
| 型號： | DS3832C-311 |
| 英文描述： | 3.3V, 32Mb Advanced NV SRAM with Clock |
| 中文描述： | 3.3，32MB的高級非易失SRAM，帶有時鐘 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 428K |
| 代理商： | DS3832C-311 |
DS3832C-311
4 of 18
NV SRAM READ MODE
The DS3832C-311 executes an NV SRAM read cycle whenever
WE0
to
WE3
(write enables) are inactive
(high), any or all of
CE0
to
CE3
(chip enables) are active (low) and
OE
(output enable) is active (low).
The unique address specified by the 20 address inputs (A
0
to A
19
) defines which of the 1,048,576 words
of data is accessed. The four chip-enable signals (
CE0
to
CE3
) determine which bytes in the addressed
word are output on data lines DQ31 to DQ0. Valid data will be output within t
ACC
(NV SRAM access
time) after the last address input signal is stable, providing that
CE
and
OE
(output enable) access times
are also satisfied. If
CE
and
OE
access times are not satisfied, then data access must be measured from
the later occurring signal (
CE
or
OE
) and the limiting parameter is either t
CO
for
CE
or t
OE
for
OE
rather
than t
ACC
.
NV SRAM WRITE MODE
The DS3832C-311 executes an NV SRAM write cycle whenever any or all of the
WE
signals (
WE0
to
WE3
) are active (low) and any of the corresponding
CE
\ signals (
CE0
to
CE3
) are active (low) after all
address inputs are stable. The later occurring falling edge of
CE
or
WE
determines the start of the write
cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be
kept valid throughout the write cycle.
WE0
to
WE3
must return to the high state for a minimum recovery
time (t
WR
) before another cycle can be initiated. The
OE
control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if output drivers are enabled (
CE
and
OE
active)
then
WE
disables the outputs in t
ODW
from its falling edge.
CLOCK READ MODE
The DS3832C-311 executes a clock read cycle whenever
WEC
(clock write enable) is inactive (high),
CEC
(clock chip enable) is active (low), and
OEC
(output enable) is active (low). The unique clock
address specified by address inputs A
0
to A
5
defines which of the 64 bytes of data is accessed. Valid data
is output within t
ACC
(clock access time) after the last address input signal is stable, providing that
CEC
and
OEC
(output enable) access times are also satisfied. If
CEC
and
OEC
access times are not satisfied,
then data access must be measured from the later occurring signal (
CEC
or
OEC
) and the limiting
parameter is either t
CO
for
CEC
or t
OE
for
OEC
rather than t
ACC
. Only addresses 0 to 3Fh are implemented
in the clock address space. Accesses to clock addresses higher than 3Fh are undefined.
CLOCK WRITE MODE
The DS3832C-311 executes a clock write cycle whenever
WEC
is active (low) and
CEC
is active (low)
after all address inputs are stable. The later occurring falling edge of
CEC
or
WEC
determines the start of
the write cycle. The write cycle is terminated by the earlier rising edge of
CEC
or
WEC
. All address
inputs must be kept valid throughout the write cycle.
WEC
must return to the high state for a minimum
recovery time (t
WR
) before another cycle can be initiated. The
OEC
control signal should be kept inactive
(high) during write cycles to avoid bus contention. However, if output drivers are enabled (
CEC
and
OEC
active) then
WEC
disables the outputs in t
ODW
from its falling edge.
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