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參數(shù)資料
| 型號(hào)： | DS3832C-311 |
| 英文描述： | 3.3V, 32Mb Advanced NV SRAM with Clock |
| 中文描述： | 3.3，32MB的高級(jí)非易失SRAM，帶有時(shí)鐘 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 428K |
| 代理商： | DS3832C-311 |
DS3832C-311
9 of 18
HI/LO—
INT
Sink or Source Current (Bit 5).
When this bit is set to logic 1 and V
CC
is applied, the
INT
output pin will source current when activated (see I
OH
spec). When this bit is set to logic 0,
INT
sinks current (see I
OL
spec).
PU/LVL—
INT
Pulse or Level (Bit 4).
When this bit is set to logic 0,
INT
is in the level mode, going to
the logic level defined by the HI/LO bit and staying there until the interrupt is cleared. When this bit is set
to logic 1,
INT
is in pulse mode, sourcing or sinking current as defined by the HI/LO bit for a minimum
of 3ms and then releasing.
WAM—Watchdog Alarm Mask (Bit 3).
When this bit is set to logic 0, the internal watchdog interrupt
signal is enabled. If IPSW is also set to logic 1, any watchdog alarm activates the
INT
output. When this
bit is set to logic 1, watchdog alarms have no effect on the internal watchdog interrupt signal or on the
INT
pin.
TDM—Time-of-Day Alarm Mask (Bit 2).
When this bit is set to logic 0, the internal time-of-day
interrupt signal is enabled. If IPSW is set to logic 0, any time-of-day alarm activates the
INT
output.
When this bit is set to logic 1, time-of-day alarms have no effect on the internal time-of-day interrupt
signal or on the
INT
pin.
WAF—Watchdog Alarm Flag (Bit 1).
This bit is set to logic 1 when a watchdog alarm occurs
(regardless of the state of the watchdog alarm mask bit WAM). WAF is read-only. This bit is reset when
either of the watchdog alarm registers is accessed. When the PU/LVL bit is in the pulse mode, this flag is
only set to logic 1 for the 3ms duration of the
INT
output pulse.
TDF—Time-of-Day Alarm Flag (Bit 0).
This bit is set to logic 1 when a time-of-day alarm occurs
(regardless of the state of the time-of-day alarm mask bit TDM). TDF is read-only. The time the alarm
occurred can be determined by reading the time-of-day alarm registers. This bit is reset to logic 0 when
any of the time-of-day alarm registers is accessed. When the PU/LVL bit is in the pulse mode, this flag is
only set to logic 1 for the 3ms duration of the
INT
output pulse.
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