參數(shù)資料
型號(hào): DS4000N
英文描述: RECT BRIDGE 15A 100V WIRE LEADS
中文描述: 數(shù)控溫補(bǔ)
文件頁(yè)數(shù): 4/16頁(yè)
文件大?。?/td> 227K
代理商: DS4000N
DS4000 Digitally Controlled TCXO
4 of 16
AC ELECTRICAL CHARACTERISTICS—2-WIRE SERIAL INTERFACE
(V
CC
= 4.75 to 5.25V, T
A
= -40 C to +85 C)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Fast mode
0
400
SCL Clock Frequency
f
SCL
Standard mode
0
100
kHz
Fast mode
1.3
Bus Free Time Between
a STOP and START
Condition
t
BUF
Standard mode
4.7
s
Fast mode (Note 7)
0.6
Hold Time (Repeated)
START Condition
t
HD:STA
Standard mode (Note 7)
4.0
s
Fast mode
1.3
Low Period of SCL
Clock
t
LOW
Standard mode
4.7
s
Fast mode
0.6
High Period of SCL
Clock
t
HIGH
Standard mode
4.0
s
Fast mode
0.6
Setup Time for a
Repeated START
Condition
t
SU:STA
Standard mode
4.7
s
Fast mode (Note 8)
0
0.9
Data Hold Time
t
HD:DAT
Standard mode (Note 8)
0
0.9
s
Fast mode (Note 9)
100
Data Setup Time
t
SU:DAT
Standard mode (Note 9)
250
ns
Fast mode (Note 9)
20 + 0.1C
B
300
Rise Time of Both SDA
and SCL
t
R
Standard mode (Note 9)
20 + 0.1C
B
1000
ns
Fast mode (Note 10)
20 + 0.1C
B
300
Fall Time of Both SDA
and SCL
t
F
Standard mode (Note 10)
20 + 0.1C
B
1000
ns
Fast mode
0.6
Setup Time for STOP
Condition
t
SU:STO
Standard mode
4.0
s
Capacitive Load for
Each Bus Line
C
B
(Note 10)
400
pF
Input Capacitance
C
I
5
pF
Note 7:
After this period, the first clock pulse is generated.
Note 8:
The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
Note 9:
A fast-mode device can be used in a standard mode system, but the requirement t
SU:DAT
>250ns must then be met. This is automatically
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
(1000 + 250 = 1250ns) before the SCL line is released.
Note 10:
C
B
: Total capacitance of one bus line in pF.
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