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| 型號(hào)： | DS80C400-FNY |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 37/97頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 75MHZ 16MB HP 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 75MHz |
| 連通性： | 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，WDT |
| 輸入/輸出數(shù)： | 64 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | ROM |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤(pán) |
| 配用： | DS80C400-KIT#-ND - EVAL KIT FOR DS80C400 |
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DS80C400 Network Microcontroller
42 of 97
Table 3. Extended Address Generation
P4CNT.5–3
P6.5
P6.4
P4.7
P4.6
P4.5
P4.4
MAX MEMORY ACCESSIBLE
per CE
000
I/O
32kB (Note 1)
001
I/O
A16
128kB
010
I/O
A17
A16
256kB
011
I/O
A18
A17
A16
512kB
100
I/O
A19
A18
A17
A16
1MB
101
I/O
A20
A19
A18
A17
A16
2MB (Note 2)
110 or 111 (default)
A21
A20
A19
A18
A17
A16
4MB (Note 3)
Table 4. Chip-Enable Generation
P6CNT.2–0
PORT 6 PIN FUNCTION
P4CNT.2–0
PORT 4 PIN FUNCTION
P6.3
P6.2
P6.1
P6.0
P4.3
P4.2
P4.1
P4.0
000 (default)
(Note 2)
I/O
000
I/O
100
I/O
CE4
100
I/O
CE0
101
I/O
CE5
CE4
101
I/O
CE1
CE0
110
I/O
CE6
CE5
CE4
110
I/O
CE2
CE1
CE0
111 (Note 2)
CE7
CE6
CE5
CE4
111 (default)
CE3
CE2
CE1
CE0
Note 1: Only 32kB of memory is accessible per chip enable for the P4CNT.5-3 = 000b setting, which means at least two chip enables are
needed to address the standard 16-bit (0–FFFFh) address range.
Note 2: When the ROM is enabled, the default memory map is reconfigured to 2MB per CE, P4CNT.5-3 = 101b, and CE4–CE7 are enabled,
P6CNT.2-0 = 111b.
Note 3: The default P4CNT.5-3 = 111b setting (4MB accessible per CE) requires only four chip enables to access the maximum 24-bit (0–
FFFFFFh) address range.
External Data Memory Addressing
Using a similar implementation as was used to expand program memory access, the DS80C400 allows up to 4MB
of data memory access through four peripheral chip enables (PCE). The Port 5 control register (P5CNT; A2h) and
Port 6 control register (P6CNT; B2h) designate the number of peripheral chip enables and the maximum amount of
addressable data memory per peripheral chip enable. Table 5 shows which port pins are converted to peripheral
chip enables, along with the maximum memory accessible through each peripheral chip enable for P5CNT, P6CNT
bit settings.
Table 5. Peripheral Chip-Enable Generation
P5CNT.2–0
P5.7
P5.6
P5.5
P5.4
P6CNT.5–3
MAX MEMORY ACSESSIBLE per PCE
000 (default)
I/O
000 (default)
32kB
100
I/O
PCE0
001
128kB
101
I/O
PCE1
PCE0
010
256kB
110
I/O
PCE2
PCE1
PCE0
011
512kB
111
PCE3
PCE2
PCE1
PCE0
100
1MB
Demultiplexed External Memory Addressing
On power-up or following any reset, the DS80C400 defaults to the traditional 8051 external memory interface, with
the address MSB presented on Port 2 and the address LSB and data multiplexed on Port 0. The multiplexed mode
requires an external latch to demultiplex the address LSB and data. The DS80C400 provides an external pin (MUX)
that, when pulled high during a power-on reset, demultiplexes the address LSB and data. If demultiplexed mode is
enabled, the address LSB is provided on Port 7 and the data on Port 0. At the expense of consuming Port 7,
demultiplexed mode eliminates the external demultiplexing latch and the delay element associated with the latch. In
some cases, the removal of this timing delay allows use of slower, less expensive external memory devices.
Table 6 shows pin assignments for the multiplexed (traditional 8051) and demultiplexed external addressing
modes.
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| DS80C400-FNY+ | 功能描述:8位微控制器 -MCU Network MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C400-KIT | 功能描述:EVAL KIT FOR DS80C400 RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 通用嵌入式開(kāi)發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:- 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類(lèi)型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤(pán)，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤(pán) 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| DS80C400-KIT# | 功能描述:開(kāi)發(fā)板和工具包 - 8051 RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類(lèi)型:USB 工作電源電壓: |
| DS80C410 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
| DS80C410_09 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
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