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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 11/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 11/88
PIN
SYMBOL
DESCRIPTION
34
33
32
31
30
29
28
27
P5.0 (AI.0)
P5.1 (AI.1)
P5.2 (AI.2)
P5.3 (AI.3)
P5.4 (AI.4)
P5.5 (AI.5)
P5.6 (AI.6)
P5.7 (AI.7)
Port 5 / AI.7–0:
– I/O / A/D inputs. Port 5 provides eight lines which can be individually
selected as open–drain psuedo–bi–directional I/O port pins or as A/D inputs. Pull–up
resistors are required when using Port 5 as an I/O port.
26
25
24
23
22
21
20
19
P6.0 (PWO.0)
P6.1 (PWO.1)
P6.2 (PWO.2)
P6.3 (PWO.3)
P6.4 (PWI.0)
P6.5 (PWI.1)
P6.6
P6.7 / SOC
Port 6 / PW0.3 – 0:
– I/O / Pulse–Width Modulated Outputs. Port 6 provides eight lines
which can all serve as psuedo–bi–directional I/O port pins with internal pull–up
resistors. Six lines can be individually selected to serve the pulse–width modulator
function indicated below:
Alternate
Function
PWO.0
PWO.1
PWO.2
PWO.3
PWI.0
PWI.1
(none)
SOC
Port
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
Description
PWM 0 output (active high drive when enabled)
PWM 1 output (active high drive when enabled)
PWM 2 output (active high drive when enabled)
PWM 3 output (active high drive when enabled)
Optional clock input for PWM channels 0 and 2
Optional clock input for PWM channels 1 and 3
External A / D start of conversion signal
69
70
71
72
73
74
75
76
P7.0 (AMI.0)
(LED.0)
P7.1 (AMI.1)
(LED.1)
P7.2 (AMI.2)
(LED.2)
P7.3 (AMI.3)
(LED.3)
P7.4 (AMI.4)
(LED.4)
P7.5 (AMI.5)
(LED.5)
P7.6 (AMI.6)
(LED.6)
P7.7 (AMI.7)
(LED.7)
Port 7 / AMI.7–0 / LED.7–0:
– I/O / Activity Monitor Inputs / LED Control. Port 7 provides
eight lines which can serve as a psuedo–bi–directional I/O port pins with internal pull–
ups or as Activity Monitor inputs. When used as Activity Monitor inputs, these pins are
typically connected to the chip select line of an external peripheral device, and can be
programmed to sense active–high or active–low signals. Any pin which is programmed
as an Activity Monitor input by setting its AMEn bit to a 1 will have its pull–up device dis-
abled and thereby function as an open–drain pin in order to eliminate unnecessary cur-
rent drain. All port 7 pins are capable of controlling LED’s.
16
15
14
13
12
11
10
9
P8.0 (KSO.0)
P8.1 (KSO.1)
P8.2 (KSO.2)
P8.3 (KSO.3)
P8.4 (KSO.4)
P8.5 (KSO.5)
P8.6 (KSO.6)
P8.7 (KSO.7)
Port 8 / KSO.7–0:
– I/O. Port 8 provides eight lines of open–drain psuedo–bi–directional
I/O port pins. Typically, these lines are used for key–scan outputs.
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