參數(shù)資料
型號： DS80CH11
英文描述： System Energy Manager
中文描述： 系統(tǒng)能量管理器
文件頁數(shù)： 19/88頁
文件大?。?/td> 598K
代理商： DS80CH11
DS80CH11
011200 19/88
3.0
CORE MICROCONTROLLER
3.1
The SEM incorporates the Dallas High Speed Micro
core which is a fully static CMOS 8051 compatible
microcontroller with a new internal architecture
designed for high performance. The higher speed
operation of the microcontroller core comes not just
from increasing the clock frequency, but from a newer,
more efficient design of the internal architecture. The
major features of the High Speed Micro Core include:
CORE MICRO OVERVIEW
4 clocks/machine cycle (8032 = 12)
Wasted cycles removed
Runs DC to 25 Mhz clock rates @ 5V
Single–cycle instruction in 160 ns
Uses less power for equivalent work
Dual data pointer
Optional variable length MOVX to access fast/slow
RAM /peripherals
3.2
All instructions in the SEM perform the same functions
as their 80C32 counterparts. Their affect on bits, flags,
and other status functions are identical. However, the
timing of each instruction is different. This applies both
in absolute and relative number of clocks.
INSTRUCTION SET SUMMARY
For absolute timing of real–time events, the timing of
software loops will need to be calculated using the table
below. However, counter/timers default to run at the
older 12 clocks per increment. Therefore, while soft-
ware runs at higher speed, timer–based events need no
modification to operate as before. Timers can be set to
run at 4 clocks per increment cycle to take advantage of
higher speed operation.
The relative time of two instructions might be different in
the new architecture than it was previously. For exam-
ple, in the original architecture, the “MOVX A, @ DPTR”
instruction and the “MOV direct, direct” instruction used
two machine cycles or 24 oscillator cycles. Therefore,
they required the same amount of time. In the GEM, the
MOVX instruction can be done in two machine cycles or
8 oscillator cycles but the “MOV direct, direct” uses
three machine cycles or 12 oscillator cycles. While both
are faster than their original counterparts, they now
have different execution times from each other. This is
because in most cases, the SEM uses one cycle for
each byte. The timing of each instruction should be
examined for familiarity with the changes. Note that a
machine cycle now requires just four clocks, and pro-
vides one ALE pulse per cycle. Many instructions
require only one cycle, but some require five. In the orig-
inal architecture, all were one or two cycles except for
MUL and DIV.
INSTRUCTION SET SUMMARY
Table 3–1
Legends:
A
Rn
direct
@Ri
–
–
–
–
Accumulator
Register R7–R0
Internal Register address
Internal Register pointed–to by R0 or R1
(except MOVX)
2’s complement offset byte
direct bit–address
8–bit constant
16–bit constant
16–bit destination address
11–bit destination address
rel
bit
#data
#data 16
addr 16
addr 11
–
–
–
–
–
–
相關(guān)PDF資料
PDF描述
DS83C520 EPROM/ROM High-Speed Micro
DS83C520-ECL EPROM/ROM High-Speed Micro
DS83C520-ENL EPROM/ROM High-Speed Micro
DS83C520-MCL EPROM/ROM High-Speed Micro
DS83C520-MNL EPROM/ROM High-Speed Micro
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS80CH11+E02 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11+E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11+E02 System Energy Managers
DS80CH11-E02 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11-E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11-E02 System Energy Managers
DS80E100 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables
DS80EP100 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables
DS80EP100_08 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables
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