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參數(shù)資料
| 型號(hào)： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 21/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 21/88
INSTRUCTION SET SUMMARY
Table 3–1
(cont’d)
Bit Manipulation
Instructions:
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
1
2
1
2
1
2
4
8
4
8
4
8
ANL C, bit
ANL C, bit
ORL C, bit
ORL C, bit
MOV C, bit
MOV bit, C
2
2
2
2
2
2
8
8
8
8
8
8
Program Branching
Instructions:
ACALL addr 11
LCALL addr 16
RET
RETI
AJMP addr 11
LJMP addr 16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
DJNZ Rn, rel
DJNZ direct, rel
2
3
1
1
2
3
2
1
2
2
2
3
12
16
16
16
12
16
12
12
12
12
12
16
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @ Ri, #data, rel
NOP
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
3
3
3
3
1
2
2
3
3
3
16
16
16
16
4
12
12
16
16
16
The Table above shows the speed for each class of
instruction. Note that many of the instructions have mul-
tiple opcodes. There are 255 opcodes for 111 instruc-
tions. Of the 255 opcodes, 159 are three times faster
than the original 80C32. While a system than empha-
sizes those instructions will see the most improvement,
the large total number that receive a three to one
improvement assure a dramatic speed increase for any
system. The speed improvement summary is provided
below.
3.3
The following table summarizes the speed improve-
ment of the High Speed Micro core over a standard 12
clock / machine cycle 8052 device.
SPEED IMPROVEMENT
#Opcodes
159
51
43
2
255
Speed Improvement
3.0 x
1.5 x
2.0 x
2.4 x
Average: 2.5
3.4
REFERENCES
The user should refer to the Dallas High Speed Micro
User’s Guide for a complete description of the instruc-
tion set including its address modes, coding, and timing
for the SEM.
INSTRUCTION SET ADDITIONAL
3.5
The High–Speed Micro has three ways of entering a
reset state:
RESET
Power–On / Fail Reset
Watchdog Timer Reset
External Reset
The operation of the CPU timing and states during a
reset are documented in the Dallas High Speed Micro
User’s Guide under the “Reset Conditions” section. The
Watchdog Timer reset is documented in the Watchdog
Timer section of the Dallas High Speed Micro User’s
Guide. The operation of the Power–On / Fail reset is
described in the Power Management section of this doc-
ument.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS83C520 | EPROM/ROM High-Speed Micro |
| DS83C520-ECL | EPROM/ROM High-Speed Micro |
| DS83C520-ENL | EPROM/ROM High-Speed Micro |
| DS83C520-MCL | EPROM/ROM High-Speed Micro |
| DS83C520-MNL | EPROM/ROM High-Speed Micro |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS80CH11+E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11+E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11+E02 System Energy Managers |
| DS80CH11-E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11-E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11-E02 System Energy Managers |
| DS80E100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
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