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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 38/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 38/88
DATA TRANSFER ON EITHER 2–WIRE BUS
Figure 6–3
SDAx
SCLx
MSB
SLAVE ADDRESS
REPEATED FOR
MULTI–BYTE XFERS
CLOCK LINE HELD LOW
XMIT: UNTIL SHIFT REG. LOAD
RECEIVE: REC. BUF. FULL
1
2
3, 6
7
8
9
ACK
1
2
3, 8
9
ACK
R/W
DIR. BIT
ACK
FROM
RECEIVER
NAK
FROM
RECEIVER
ACK
FROM
RECEIVER
CONDITION
STOP
REPEAT
START
STOP OR
REPEAT START
CONDITION
START
CONDITION
6.3.1
In the master transmit mode, the SEM is configured as a
master device and transfers a number of data bytes to a
slave receiver. A timing diagram in Figure 6–4 illus-
trates the interaction between the firmware and hard-
ware with respect to events on the 2–Wire bus.
Master Transmit
The master transmit mode can now be entered by set-
ting the STAx bit. The 2–Wire port logic will test the
2–Wire bus and generate a start condition as soon as
the bus is free. As soon as the start condition is trans-
mitted, the TSTAx flag will be set. In addition, the X/Rx
bit will be set to a 1, indicating transmit operation is in
effect.
In response to TSTAx being set, the firmware can now
write to the transmit buffer an initial byte for the message
as follows:
7
6
5
4
3
2
1
0
7–bit Slave Address
0
MASTER TRANSMIT OPERATION TIMING
Figure 6–4
éé
éé
DATA
SLAVE ADDR.
R/W
S
A
A/A
Sr
A
DATA
éé
éé
SLAVE ADDR.
DATA
R/W
A
P
SDAx/SCLx
STAx BIT
X/Rx BIT
XMIT BUF
WRITE
TSTAx BIT
TXIx BIT
ACKSx BIT
STOx BIT
ACTION TAKEN BY FIRMWARE
MASTER TO SLAVE XFER
ALTERNATIVE CONDITION
SLAVE TO MASTER XFER
A = ACKNOWLEDGE (SDAx LOW)
A = NEGATIVE ACKNOWLEDGE (SDAx HIGH)
S = START CONDITION
Sr = REPEAT START CONDITION
P = STOP CONDITION
0
0
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