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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 53/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 53/88
ACTIVITY MONITOR INPUTS
Figure 8–1
AMP.n
RD_P7.n
AMQ.n
WR_“0”_AMF.n
BIT
BIT
AMI.n
AME.n
BIT
RD_AMF.n
ACTIVITY
MONITOR
INTERRUPT
IOR
IOW
When one or more peripheral devices have been pow-
ered down due to inactivity, it may be desirable at that
time to enable interrupts to at least those devices.
When an access is attempted by the host, the SEM can
take the appropriate action to apply power to the periph-
eral. During such time, the SEM can activate the SMI1
or SMI2 interrupt by writing to a power management
host interface output buffer register with a status word
reflecting the current condition.
8.3
AME – ACTIVITY MONITOR ENABLE REGISTER
AME; SFR ADDR.=092H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AME7
AME6
AME5
AME4
AME3
AME2
AME1
AME0
Read/Write Access: Unrestricted.
Initialization: 00h on any type of reset
When an AME bit is set to 1, it enables the correspond-
ing line of Port 7 as an activity monitor interrupt source.
An interrupt condition will exist when the associated
activity monitor flag bit is set (see below). When AME is
cleared to 0, the associated pin is disabled as an inter-
rupt source. The associated Port 7 latch bit must be set
to 1 when a pin is to be programmed as an activity moni-
tor input.
8.4
AMQ – ACTIVITY MONITOR QUALIFIER REGISTER
AMQ; SFR ADDR.=093H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AMQ7
AMQ6
AMQ5
AMQ4
AMQ3
AMQ2
AMQ1
AMQ0
Read/Write Access: Unrestricted.
Initialization: 00h on any type of reset
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