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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 9/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 9/88
2.1
PIN FUNCTION SUMMARY
PIN
SYMBOL
DESCRIPTION
36
A0
Command / Data Select:
Input. Address input used by the host processor in data
transfers to the keyboard controller and power management #1 and #2 interface ports to
indicate whether the transfer is command (A0=1) or data (A0=0).
43
AGND
Analog Ground.
106
ALE
Address Latch Enable:
Output. This signal functions as a clock to latch the external
address LSB from the multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external 373 family transparent latch. ALE has a
pulse width of 1.5 XTAL1 cycles and a period of 4 XTAL1 cycles. ALE is forced high
when the SEM is in a Reset condition.
46
AVCC
Analog VCC.
17
35
86
117
GND
Digital circuit ground.
47
HGND
Host Interface Ground:
68
HVCC
Host Interface VCC:
38
IOR
I/O Read:
Input. I/O Read is used to signal a read operation is in effect on the host
address/data bus.
37
IOW
I/O Write:
Input. I/O Write is used to signal a write operation is in effect on the host
address/data bus.
42
KBCS
Keyboard Chip Select:
(Input, active low). This is a chip select signal used to enable
the keyboard control host interface port.
40
KBOBF
Keyboard Output Buffer Full:
(Output, active high). This signal is set when the key-
board control host interface data buffer contains data to be read by the host. KBOBF will
be driven low when host reads the keyboard control data buffer register.
56
57
108
NC
No Connection.
121
122
123
124
125
126
127
128
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
Port 0 / Address/Data Outputs 7–0:
I/O. Port 0 is an open–drain 8–bit bi–directional
I/O port. As an alternate function Port 0 can function as the multiplexed address/data
bus to access off–chip memory. During the time when ALE is high, the LSB of a memory
address is presented. When ALE falls to a logic 0, the port transitions to a bi–directional
data bus. This bus is used to read external ROM and read/write external RAM memory
or peripherals. When used as a memory bus, the port provides active high drivers. The
reset condition of Port 0 is tri–state. Pull–up resistors are required when using Port 0 as
an I/O port.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS80CH11+E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11+E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11+E02 System Energy Managers |
| DS80CH11-E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11-E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11-E02 System Energy Managers |
| DS80E100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
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