參數(shù)資料
型號: DS83C520-QCL
英文描述: EPROM/ROM High-Speed Micro
中文描述: 存儲器/ ROM的高速微
文件頁數(shù): 31/45頁
文件大?。?/td> 1415K
代理商: DS83C520-QCL
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
31 of 45
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 4.5V, T
A
= -40°C to +85°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Transition Current from 1 to 0 Ports 1, 2, 3
at 2V
Input Leakage Port 0, and
EA
pins, I/O
Mode
Input Leakage Port 0, Bus Mode
RST Pulldown Resistance
I
TL
-800
μA
9
I
L
-10
+10
μA
11
I
L
-300
50
+300
200
μA
k
10
R
RST
Note 1:
Note 2:
Note 3:
Note 4:
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
All voltages are referenced to ground.
Active current measured with 33MHz clock source on XTAL1, V
CC
= RST = 5.5V, other pins disconnected.
Idle mode current measured with 33MHz clock source on XTAL1, V
CC
= 5.5V, RST at ground, other pins
disconnected.
Stop mode current measured with XTAL1 and RST grounded, V
CC
= 5.5V, all other pins disconnected.
When addressing external memory. This specification only applies to the first clock cycle following the transition.
RST = V
CC
. This condition mimics operation of pins in I/O mode. Port 0 is tri-stated in reset and when at a logic high
state during I/O mode.
During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in
transition mode.
Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately
2V.
0.45 < V
IN
< V
CC
. Not a high-impedance input. This port is a weak address holding latch in Bus Mode. Peak current
occurs near the input transition point of the latch, approximately 2V.
0.45 < V
IN
< V
CC
. RST = V
CC
. This condition mimics operation of pins in I/O mode.
This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port
latch bit is set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin will also
have to overcome the transition current.
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
TYPICAL I
CC
vs. FREQUENCY
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