參數(shù)資料
型號(hào)： DSD1608PAH
英文描述： 8-CHANNEL, ENHANCED MULTIFORMAT, DELTA-SIGMA, DIGITAL-TO-ANALOG CONVERTER
中文描述： 8通道，增強(qiáng)多格式，Δ-Σ，數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù)： 30/41頁
文件大?。?/td> 293K
代理商： DSD1608PAH
DSD1608
SLES040
–
JUNE 2002
www.ti.com
30
D/A OUTPUT FILTER CIRCUITS: POST-LOW-PASS FILTER
The DSD1608 requires a third- or second-order analog low-pass filter to achieve the frequency response
recommended by the SACD standard and reduce the out-of-band noise produced by the delta-sigma modulator.
Figure 32 shows the recommended external low-pass filter circuit. This circuit is a third-order Butterworth filter using
the Sallen-Key circuit arrangement. The filter response and corner frequency are determined by the frequency
response recommended by the SACD standard. Figure 32 lists the standard values for resistors and capacitors
corresponding with the DSD digital filter on DSD1608. This filter can be used in either the PCM or the DSD modes.
C1
1500 pF
R5
10 k
R1
2.7 k
R2
6.8 k
C2
680 pF
R3
15 k
C3
100 pF
R4
10 k
–
+
Figure 32. Post-Low-Pass Filter Circuit
TDMCA FORMAT
The DSD1608 supports the time division multiplexed command and audio data (TDMCA) format to reduce any host
control serial interface. The TDMCA format is designed for not only McBSP of TI DSPs but also any programmable
devices. The TDMCA format can transfer not only audio data but also command data so that it can be used with any
kind of device that supports the TDMCA format. The TDMCA frame consists of a command field, extended command
field, and some audio data fields. The audio data are transported to IN devices (such as DAC) and/or from OUT
devices (such as ADC). The DSD1608 is an IN device. PLRCK and PBCK are shared both IN and OUT devices so
that the sample frequency must be united in one system. The TDMCA mode supports a maximum of 30 device IDs.
The maximum number of audio channel depends on the PBCK frequency.
TDMCA Mode Determination
The DSD1608 recognizes the TDMCA mode by receiving PLRCK which pulse width is two PBCK clocks. The
DSD1608 goes into the TDMCA after two continuous TDMCA frames. Figure 33 shows the PLRCK and PBCK timing
required for the TDMCA mode. Any TDMCA commands can be issued the next TDMCA frame after entering the
TDMCA mode. If operation in the TDMCA mode operation is not required, PLRCK must be a 50%-duty-cycle square
wave.
Pre TDMCA Frame
PBCK
PLRCK
2PBCK
TDMCA Frame
Command
Accept
Figure 33. PLRCK and PBCK Timing for the TDMCA Mode
相關(guān)PDF資料
PDF描述
DSD1608PAHR 8-CHANNEL, ENHANCED MULTIFORMAT, DELTA-SIGMA, DIGITAL-TO-ANALOG CONVERTER
DSD1700 Direct Stream Digital⑩ DSD⑩ TM Audio DIGITAL-TO-ANALOG CONVERTER
DSD1700E DIODE - SCHOTTKY, 3A (SMT)
DSD1792 24 bit 192 khz SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
DSD1792DB 24 bit 192 khz SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
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