參數(shù)資料
型號： DSD1608PAHR
英文描述： 8-CHANNEL, ENHANCED MULTIFORMAT, DELTA-SIGMA, DIGITAL-TO-ANALOG CONVERTER
中文描述： 8通道，增強(qiáng)多格式，Δ-Σ，數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù)： 15/41頁
文件大?。?/td> 293K
代理商： DSD1608PAHR
DSD1608
SLES040
–
JUNE 2002
www.ti.com
15
t(SCKH)
System Clock
(PSCK, DSCK)
t(SCKL)
2 V
0.8 V
H
L
t(SCY)
SYMBOL
PARAMETERS
MIN
MAX
UNIT
t(SCY)
t(SCKH)
t(SCKL)
System clock pulse cycle time
13
ns
System clock pulse duration high
0.4 tSCY
0.4 tSCY
ns
System clock pulse duration low
ns
Figure 20. System Clock Input Timing
Power-On and External Reset Functions
The DSD1608 includes a power-on reset function. Figure 21 shows the operation of this function. With V
DD
> 2 V,
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V
DD
> 2 V. After the initialization period, the DSD1608 is set to its reset default state, as described in the
mode control
register
section of this data sheet. The DSD1608 also includes an external reset capability using the RST input (pin
36). This allows an external controller or master reset circuit to force the DSD1608 to initialize to its reset state.
Figure 22 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. When
the RST pin is set to a logic 0 state, the DSD1608 is initialized. The RST pin is then set to a logic 1 state, thus starting
the initialization sequence, which requires 1024 system clock periods.
Reset
Reset Removal
1024 System Clocks
VDD
2.4 V
2 V
1.6 V
Internal Reset
System Clock
(PSCK)
Figure 21. Power-On Reset Timing
Reset
Reset Removal
1024 System Clocks
Internal Reset
System Clock
RST (Pin 36)
t(RST)
50% of VDD
SYMBOL
PARAMETERS
MIN
MAX
UNIT
t(RST)
Reset pulse duration low
20
ns
Figure 22. External Reset Timing
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