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參數(shù)資料
| 型號： | DSD1608PAHR |
| 英文描述： | 8-CHANNEL, ENHANCED MULTIFORMAT, DELTA-SIGMA, DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 8通道，增強(qiáng)多格式，Δ-Σ，數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 35/41頁 |
| 文件大?。?/td> | 293K |
| 代理商： | DSD1608PAHR |
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DSD1608
SLES040
–
JUNE 2002
www.ti.com
35
Register Write/Read Operation
The command supports register write and read operations. If the command requests to read one register, the read
data is transferred on PDO during the data phase portion of the timing cycle. The PDI signal can be retrieved on the
positive edge of PBCK and the PDO signal is driven on the negative edge of PBCK. The PDO is activated one cycle
early due to compensate for the output delay caused by high impedance. Figure 39 shows the TDMCA write and read
timing.
PBCK
PDI
PDO
PDOEN
(Internal)
1 PBCK Early
Read Mode and Proper Register ID
Write Data Retrieved, if Write Mode
Read Data Driven, if Read Mode
Register ID Phase
Data Phase
Figure 39. TDMCA Write and Read Operation Timing
TDMCA Mode Operation
DCO specifies the owner of the next audio channel in TDMCA operation. When one device retrieves its own audio
channel data, the DCO becomes HIGH during last audio channel period. Figure 40 shows the DCO output timing
during a TDMCA-mode operation. The host controller is not affected by the behavior of DCI and DCO. DCO indicates
the last audio channel of each device. Therefore, DCI means that the next audio channel is allocated.
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