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參數(shù)資料
| 型號(hào)： | DSF10K |
| 廠(chǎng)商： | Altera Corporation |
| 英文描述： | EMBEDDED PROGRAMMABLE LOGIC FAMILY |
| 中文描述： | 嵌入式可編程邏輯系列 |
| 文件頁(yè)數(shù)： | 36/138頁(yè) |
| 文件大?。?/td> | 2116K |
| 代理商： | DSF10K |
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36
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
ClockLock &
ClockBoost
Features
To support high-speed designs, selected FLEX 10K devices offer optional
ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)
that is used to increase design speed and reduce resource usage. The
ClockLock circuitry uses a synchronizing PLL that reduces the clock delay
and skew within a device. This reduction minimizes clock-to-output and
setup times while maintaining zero hold times. The ClockBoost circuitry,
which provides a clock multiplier, allows the designer to enhance device
area efficiency by sharing resources within the device. The ClockBoost
feature allows the designer to distribute a low-speed clock and multiply
that clock on-device. Combined, the ClockLock and ClockBoost features
provide significant improvements in system performance and
bandwidth.
The ClockLock and ClockBoost features in FLEX 10K devices are enabled
through the MAX+PLUS II software. External devices are not required to
use these features. The output of the ClockLock and ClockBoost circuits is
not available at any of the device pins.
The ClockLock and ClockBoost circuitry locks onto the rising edge of the
incoming clock. The circuit output can only drive the clock inputs of
registers; the generated clock cannot be gated or inverted.
The dedicated clock pin (
GCLK1
) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the
device.
In designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to
GCLK1
. With the
MAX+PLUS II software,
GCLK1
can feed both the ClockLock and
ClockBoost circuitry in the FLEX 10K device. However, when both circuits
are used, the other clock pin (
GCLK0
) cannot be used. Figure 17 shows a
block diagram of how to enable both the ClockLock and ClockBoost
circuits in the MAX+PLUS II software. The example shown is a schematic,
but a similar approach applies for designs created in AHDL, VHDL, and
Verilog HDL. When the ClockLock and ClockBoost circuits are used
simultaneously, the input frequency parameter must be the same for both
circuits. In
Figure 17
, the input frequency must meet the requirements
specified when the ClockBoost multiplication factor is two.
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