參數(shù)資料
型號： DSPIC33FJ12GP202T-I/ML
廠商： Microchip Technology
文件頁數(shù)： 5/90頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 12K 28QFN
產(chǎn)品培訓模塊： Asynchronous Stimulus
標準包裝： 1,600
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 21
程序存儲器容量： 12KB（12K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-VQFN 裸露焊盤
包裝： 帶卷 (TR)
配用： AC164336-ND - MODULE SOCKET FOR PM3 28/44QFN
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱： DSPIC33FJ12GP202T-I/MLTR
2005 Microchip Technology Inc.
Preliminary
DS70155C-page 11
dsPIC33F
3.3
Data Address Space
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
3.3.1
X AND Y DATA SPACES
The X data space is used by all instructions and
supports all addressing modes. There are separate
read and write data buses for X data space. The X read
data bus is the read data path for all instructions that
view data space as combined X and Y address space.
It is also the X data prefetch path for the dual operand
DSP instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N
and MSC) to
provide two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing for all instructions, subject to addressing
mode restrictions. Bit-Reversed Addressing is only
supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent (an example is shown in Figure 3-3)
and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words, though the
implemented memory locations vary from one device to
another.
3.3.2
DMA RAM
Every dsPIC33F device contains 2 Kbytes of DMA RAM
located at the end of Y data space. Memory locations in
the DMA RAM space are accessible simultaneously by
the CPU and the DMA Controller module. DMA RAM is
utilized by the DMA Controller to store data to be
transferred to various peripherals using DMA, as well as
data transferred from various peripherals using DMA.
When the CPU and the DMA Controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
3.3.3
DATA SPACE WIDTH
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
Figure 3-3 depicts a sample data space memory map
for the dsPIC33F device with 33 Kbytes of RAM.
3.3.4
DATA ALIGNMENT
To
help
maintain
backward
compatibility
with
PICmicro devices and improve data space memory
usage efficiency, the dsPIC33F instruction set supports
both word and byte operations. Data is aligned in data
memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word which contains the byte, using the Least
Significant bit (LSb) of any EA to determine which byte
to select.
As a consequence of this byte accessibility, all effective
address
calculations
are
internally
scaled.
For
example, the core would recognize that Post-Modified
Register Indirect Addressing mode, [Ws++], will result
in a value of Ws + 1 for byte operations and Ws + 2 for
word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported.
Should a misaligned read or write be attempted, a trap
will then be executed, allowing the system and/or user
to examine the machine state prior to execution of the
address Fault.
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