參數(shù)資料
型號(hào): DSPIC33FJ32MC204T-I/ML
廠商: Microchip Technology
文件頁(yè)數(shù): 10/76頁(yè)
文件大小: 0K
描述: IC DSPIC MCU/DSP 32K 44QFN
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 1,600
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 帶卷 (TR)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱: DSPIC33FJ32MC204T-I/MLTR
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DS70283K-page 18
2007-2012 Microchip Technology Inc.
3.3
Special MCU Features
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
features a 17-bit by 17-bit single-cycle multiplier that is
shared by both the MCU ALU and DSP engine. The
multiplier can perform signed, unsigned and mixed-sign
multiplication. Using a 17-bit by 17-bit multiplier for 16-bit
by 16-bit multiplication not only allows you to perform
mixed-sign multiplication, it also achieves accurate results
for special operations, such as (-1.0) x (-1.0).
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
supports 16/16 and 32/16 divide operations, both
fractional and integer. All divide instructions are iterative
operations. They must be executed within a REPEAT loop,
resulting in a total execution time of 19 instruction cycles.
The divide operation can be interrupted during any of
those 19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1:
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU CORE BLOCK DIAGRAM
Instruction
Decode and
Control
PCH
PCL
Program Counter
16-bit ALU
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
EA MUX
Interrupt
Controller
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Control Signals
to Various Blocks
L
ite
ra
lD
at
a
16
To Peripheral Modules
Data Latch
Address
Latch
16
X RAM
Y RAM
Address Generator Units
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
23
16
8
PSV and Table
Data Access
Control Block
16
Program Memory
Data Latch
Address Latch
16
24
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