參數(shù)資料
型號(hào): EL5420CLZ-T7
廠商: INTERSIL CORP
元件分類: 運(yùn)算放大器
英文描述: 12MHz Rail-to-Rail Input-Output Op Amps
中文描述: QUAD OP-AMP, 12000 uV OFFSET-MAX, 8 MHz BAND WIDTH, QCC16
封裝: ROHS COMPLIANT, QFN-16
文件頁(yè)數(shù): 4/13頁(yè)
文件大?。?/td> 275K
代理商: EL5420CLZ-T7
12
EL5220C, EL5420C
12MHz Rail-to-Rail Input-Output Op Amps
E
L
52
20
C
,E
L
54
20
C
Figure 4. Package Power Dissipation vs
Ambient Temperature
Figure 5. Package Power Dissipation vs
Ambient Temperature
Unused Amplifiers
It is recommended that any unused amplifiers in a dual
and a quad package be configured as a unity gain fol-
lower. The inverting input should be directly connected
to the output and the non-inverting input tied to the
ground plane.
Driving Capacitive Loads
The EL5220C and EL5420C can drive a wide range of
capacitive loads. As load capacitance increases, how-
ever, the -3dB bandwidth of the device will decrease and
the peaking increase. The amplifiers drive 10pF loads in
parallel with 10k
with just 1.5dB of peaking, and
100pF with 6.4dB of peaking. If less peaking is desired
in these applications, a small series resistor (usually
between 5
and 50) can be placed in series with the
output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
“snubber” circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values
of 150
and 10nF are typical. The advantage of a snub-
ber is that it does not draw any DC load current or
reduce the gain
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5220C and EL5420C can provide gain at high
frequency. As with any high-frequency device, good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly rec-
ommended, lead lengths should be as short as possible
and the power supply pins must be well bypassed to
reduce the risk of oscillation. For normal single supply
operation, where the VS- pin is connected to ground, a
0.1F ceramic capacitor should be placed from VS+ to
pin to VS- pin. A 4.7F tantalum capacitor should then
be connected in parallel, placed in the region of the
amplifier. One 4.7F capacitor may be used for multiple
devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are
to be used.
MAX TJ=125°C
606mW
833mW
400
800
Po
w
er
Di
ss
ip
at
io
n
(m
W
)
Ambient Temperature (°C)
0
1200
1000
600
200
25
50
75
100
125
150
85
SO14
θJA=120°C/W
MSOP8
θJA=206°C/W
JEDEC JESD51-3 and SEMI G42-88 (Single Layer) Test
Board
667mW
485mW
TSSOP14
θJA=165°C/W
LPP16
θJA=150°C/W
JEDEC JESD51-7 High Effective Thermal Conductivity (4-
Layer) Test Board
(LPP exposed diepad soldered to PCB per JESD51-5)
3
2.5
2
1.5
1
0.5
0
25
50
75
100
125
150
Ambient Temperature (°C)
Po
w
er
Di
ss
ip
at
io
n
(W
)
85
2.500W
LPP
16
40°
C/W
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