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| 型號： | EP1810 |
| 廠商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件） |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 227K |
| 代理商： | EP1810 |
Altera Corporation
981
AN 78: Understanding MAX 5000 & Classic Timing
For Classic devices, the second bit of the
7483
adder macrofunction,
s2
,
requires shared expanders. The equations are as follows:
S2
_EQ003 = A2 & B1 & B2 & C0
# A1 & A2 & B2 & !_LC017
# !A2 & B1 & !B2 & C0
# A1 & !A2 & !B2 & !_LC017
# !A2 & !B1 & B2 & !_LC018
# !A1 & !A2 & B2 & !C0
# A2 & !B1 & !B2 & !_LC018
# !A1 & A2 & !B2 & !C0;
_LC017 = LCELL(_EQ010);
_EQ010 = !B1 & !C0;
_LC018 = LCELL(_EQ011);
_EQ011 = A1 & C0;
:
= LCELL(_EQ003);
Figure 8
shows how you can map the logic structure onto the Classic
architecture with these equations. The timing delay for
s2
in Classic
devices is shown below:
t
IN
+ t
LAD
+ t
FD
+ t
LAD
+ t
OD
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