參數(shù)資料
型號(hào)： EP1C6T144I7
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁數(shù)： 62/94頁
文件大小： 1138K
代理商： EP1C6T144I7
62
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Note to
Table 18
:
(1)
Bus hold and weak pull-up resistor features override the high-impedance state of
HIGHZ
,
CLAMP
, and
EXTEST
.
Table 18. Cyclone JTAG Instructions
JTAG Instruction
Instruction Code
Description
SAMPLE
/
PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
Selects the 32-bit USERCODE register and places it between the
TDI
and
TDO
pins, allowing the USERCODE to be serially shifted
out of
TDO
.
Selects the IDCODE register and places it between
TDI
and
TDO
,
allowing the IDCODE to be serially shifted out of
TDO
.
Places the 1-bit bypass register between the
TDI
and
TDO
pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring a Cyclone device via the JTAG port with a
MasterBlaster
TM
or ByteBlasterMV
TM
download cable, or when
using a Jam File or Jam Byte-Code File via an embedded
processor.
Emulates pulsing the
nCONFIG
pin low to trigger reconfiguration
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, after, or during
configuration. Stops configuration if executed during configuration.
Once issued, the
CONFIG_IO
instruction will hold
nSTATUS
low to
reset the configuration device.
nSTATUS
is held low until the device
is reconfigured.
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
EXTEST
(1)
00 0000 0000
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE
00 0000 0110
HIGHZ
(1)
00 0000 1011
CLAMP
(1)
00 0000 1010
ICR instructions
PULSE_NCONFIG
00 0000 0001
CONFIG_IO
00 0000 1101
SignalTap II
instructions
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1C6T144I7N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone I 598 LABs 98 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1F 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY
EP1F-B3G1 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY
EP1FB3G1S 制造商:World Products 功能描述:Electromechanical Relay SPDT 25A 12VDC 225Ohm Through Hole
EP1F-B3G1T 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY
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