參數(shù)資料
型號(hào)： EP1C6T144I8
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁(yè)數(shù)： 75/94頁(yè)
文件大?。?/td> 1138K
代理商： EP1C6T144I8
Altera Corporation
75
Preliminary Information
Cyclone FPGA Family Data Sheet
Table 41. IOE Internal Timing Microparameter Descriptions
Symbol
Parameter
t
SU
t
H
t
CO
t
PIN2COMBOUT_R
t
PIN2COMBOUT_C
t
COMBIN2PIN_R
t
COMBIN2PIN_C
t
CLR
t
PRE
t
CLKHL
IOE input and output register setup time before clock
IOE input and output register hold time after clock
IOE input and output register clock-to-output delay
Row input pin to IOE combinatorial output
Column input pin to IOE combinatorial output
Row IOE data input to combinatorial output pin
Column IOE data input to combinatorial output pin
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
Table 42. M4K Block Internal Timing Microparameter Descriptions
Symbol
Parameter
t
M4KRC
t
M4KWC
t
M4KWERESU
t
M4KWEREH
t
M4KBESU
t
M4KBEH
t
M4KDATAASU
t
M4KDATAAH
t
M4KADDRASU
t
M4KADDRAH
t
M4KDATABSU
t
M4KDATABH
t
M4KADDRBSU
t
M4KADDRBH
t
M4KDATACO1
t
M4KDATACO2
t
M4KCLKHL
t
M4KCLR
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
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