參數(shù)資料
型號(hào)： EP1C6T240C7
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁(yè)數(shù)： 43/94頁(yè)
文件大?。?/td> 1138K
代理商： EP1C6T240C7
Altera Corporation
43
Preliminary Information
Cyclone FPGA Family Data Sheet
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with
a variable duty cycle. This feature is supported on each PLL post-scale
counter (g0, g1, e). The duty cycle setting is achieved by a low- and high-
time count setting for the post-scale dividers. The Quartus II software uses
the frequency input and the required multiply or divide rate to determine
the duty cycle choices.
Control Signals
There are three control signals for clearing and enabling PLLs and their
outputs. The designer can use these signals to control PLL
resynchronization and the ability to gate PLL output clocks for low-power
applications.
The
pllenable
signal enables and disables PLLs. When the
pllenable
signal is low, the clock output ports are driven by ground and all the PLLs
go out of lock. When the
pllenable
signal goes high again, the PLLs
relock and resynchronize to the input clocks. An input pin or LE output
can drive the
pllenable
signal.
The
areset
signals are reset/resynchronization inputs for each PLL.
Cyclone devices can drive these input signals from input pins or from LEs.
When
areset
is driven high, the PLL counters will reset, clearing the PLL
output and placing the PLL out of lock. When driven low again, the PLL
will resynchronize to its input as it relocks.
The
pfdena
signals control the phase frequency detector (PFD) output
with a programmable gate. If you disable the PFD, the VCO will operate
at its last set value of control voltage and frequency with some drift, and
the system will continue running when the PLL goes out of lock or the
input clock disables. By maintaining the last locked frequency, the system
has time to store its current settings before shutting down. The designer
can either use their own control signal or gated locked status signals to
trigger the
pfdena
signal.
f
For more information on Cyclone PLLs, see
AN 251: Using PLLs in Cyclone
Devices.
相關(guān)PDF資料
PDF描述
EP1C6T240C8 Cyclone FPGA Family
EP1C6T240I6 Cyclone FPGA Family
EP1C6T240I7 Cyclone FPGA Family
EP1C6T240I8 Cyclone FPGA Family
EP1C6T256C6 Cyclone FPGA Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1F 制造商:NEC 制造商全稱(chēng):NEC 功能描述:HIGH HEAT RESISTIVITY
EP1F-B3G1 制造商:NEC 制造商全稱(chēng):NEC 功能描述:HIGH HEAT RESISTIVITY
EP1FB3G1S 制造商:World Products 功能描述:Electromechanical Relay SPDT 25A 12VDC 225Ohm Through Hole
EP1F-B3G1T 制造商:NEC 制造商全稱(chēng):NEC 功能描述:HIGH HEAT RESISTIVITY
EP1F-B3G1TT 制造商:NEC 制造商全稱(chēng):NEC 功能描述:HIGH HEAT RESISTIVITY
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*