參數(shù)資料
型號: EP1C6T240I8
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁數(shù): 74/94頁
文件大小: 1138K
代理商: EP1C6T240I8
74
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under worst-
case voltage and junction temperature conditions.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density.
Tables 40
through
43
describe the Cyclone
device internal timing microparameters for LEs, IOEs, M4K memory
structures, and MultiTrack interconnects.
Table 39. Cyclone Device Timing Model Status
Device
Preliminary
Final
EP1C3
v
EP1C4
v
EP1C6
v
EP1C12
v
EP1C20
v
Table 40. LE Internal Timing Microparameter Descriptions
Symbol
Parameter
t
SU
t
H
t
CO
t
LUT
t
CLR
t
PRE
t
CLKHL
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinatorial LUT delay for data-in to data-out
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
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