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參數(shù)資料
| 型號： | EP1C6T256I8 |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family |
| 中文描述： | 氣旋FPGA系列 |
| 文件頁數(shù)： | 40/94頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | EP1C6T256I8 |
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40
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Table 10
shows the global clock network sources available in Cyclone
devices.
Notes to
Table 10
:
(1)
EP1C3 devices only have one PLL (PLL 1).
(2)
EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins
CLK1
and
CLK3
.
(3)
EP1C3 devices in the 100-pin TQFP package do not have the
DPCLK0
,
DPCLK1
, or
DPCLK5
pins.
Clock Multiplication & Division
Cyclone PLLs provide clock synthesis for PLL output ports using
m
/(
n
×
post scale counter) scaling factors. The input clock is divided by a
pre-scale divider,
n
, and is then multiplied by the
m
feedback factor. The
control loop drives the VCO to match f
IN
×
(
m
/
n
). Each output port has a
unique post-scale counter to divide down the high-frequency VCO. For
multiple PLL outputs with different frequencies, the VCO is set to the
least-common multiple of the output frequencies that meets its frequency
specifications. Then, the post-scale dividers scale down the output
frequency for each output port. For example, if the output frequencies
required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the
least-common multiple in the VCO’s range).
Table 10. Global Clock Network Sources
Source
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
PLL Counter
Output
PLL1 G0
v
v
PLL1 G1
v
v
PLL2 G0
(1)
v
v
PLL2 G1
(1)
v
v
Dedicated
Clock Input
Pins
CLK0
v
v
CLK1
(2)
v
v
CLK2
v
v
CLK3
(2)
v
v
Dual-Purpose
Clock Pins
DPCLK0
(3)
v
DPCLK1
(3)
v
DPCLK2
v
DPCLK3
v
DPCLK4
v
DPCLK5
(3)
v
DPCLK6
v
DPCLK7
v
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