參數(shù)資料
型號: EP1C6T256I8
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁數(shù): 78/94頁
文件大?。?/td> 1138K
代理商: EP1C6T256I8
78
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
External Timing Parameters
External timing parameters are specified by device density and speed
grade.
Figure 38
shows the timing model for bidirectional IOE pin timing.
All registers are within the IOE.
Table 46. M4K Block Internal Timing Microparameters
Symbol
-6
-7
-8
Unit
Min
Max
Min
Max
Min
Max
t
M4KRC
t
M4KWC
t
M4KWERESU
t
M4KWEREH
t
M4KBESU
t
M4KBEH
t
M4KDATAASU
t
M4KDATAAH
t
M4KADDRASU
t
M4KADDRAH
t
M4KDATABSU
t
M4KDATABH
t
M4KADDRBSU
t
M4KADDRBH
t
M4KDATACO1
t
M4KDATACO2
t
M4KCLKHL
t
M4KCLR
4,379
2,910
5,035
3,346
5,691
3,783
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
72
43
72
43
72
43
72
43
72
43
72
43
82
49
82
49
82
49
82
49
82
49
82
49
93
55
93
55
93
55
93
55
93
55
93
55
621
4,351
714
5,003
807
5,656
105
286
120
328
136
371
Table 47. Routing Delay Internal Timing Microparameters
Symbol
-6
-7
-8
Unit
Min
Max
Min
Max
Min
Max
t
R4
t
C4
t
LOCAL
261
338
244
300
388
281
339
439
318
ps
ps
ps
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