參數(shù)資料
型號: EP1C6T324C7
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁數(shù): 23/94頁
文件大?。?/td> 1138K
代理商: EP1C6T324C7
Altera Corporation
23
Preliminary Information
Cyclone FPGA Family Data Sheet
Embedded
Memory
The Cyclone embedded memory consists of columns of M4K memory
blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while
EP1C12 and EP1C20 devices have two columns (see
Table 1 on page 1
for
total RAM bits per density). Each M4K block can implement various types
of memory with or without parity, including true dual-port, simple dual-
port, and single-port RAM, ROM, and FIFO buffers. The M4K blocks
support the following features:
4,608 RAM bits
200 MHz performance
True dual-port memory
Simple dual-port memory
Single-port memory
Byte enable
Parity bits
Shift register
FIFO buffer
ROM
Mixed clock mode
Memory Modes
The M4K memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K blocks offer a true dual-port mode to support any
combination of two-port operations: two reads, two writes, or one read
and one write at two different clock frequencies.
Figure 12
shows true
dual-port memory.
Figure 12. True Dual-Port Memory Configuration
In addition to true dual-port memory, the M4K memory blocks support
simple dual-port and single-port RAM. Simple dual-port memory
supports a simultaneous read and write. Single-port memory supports
non-simultaneous reads and writes.
Figure 13
shows these different M4K
RAM memory port configurations.
data
A
[
address
A
[
wren
A
clock
A
clocken
A
q
A
[
aclr
A
data
B
[
address
B
[
wren
B
clock
B
clocken
B
q
B
[
aclr
B
A
B
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