參數(shù)資料
型號(hào)： EP1C6T324C7
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁(yè)數(shù)： 80/94頁(yè)
文件大小： 1138K
代理商： EP1C6T324C7
80
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Table 48
shows the external I/O timing parameters when using global
clock networks.
Notes to
Table 48
:
(1)
These timing parameters are sample-tested only.
(2)
These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II
software to verify the external timing for any pin.
Table 48. Cyclone Global Clock External I/O Timing Parameters
Notes (1)
,
(2)
Symbol
Parameter
Conditions
t
INSU
Setup time for input or bidirectional pin using IOE input
register with global clock fed by
CLK
pin
Hold time for input or bidirectional pin using IOE input
register with global clock fed by
CLK
pin
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by
CLK
pin
Synchronous column IOE output enable register to output
pin disable delay using global clock fed by
CLK
pin
Synchronous column IOE output enable register to output
pin enable delay using global clock fed by
CLK
pin
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock enhanced PLL with default
phase setting
Synchronous column IOE output enable register to output
pin disable delay using global clock fed by enhanced PLL
with default phase setting
Synchronous column IOE output enable register to output
pin enable delay using global clock fed by enhanced PLL
with default phase setting
t
INH
t
OUTCO
C
LOAD
= 10 pF
t
XZ
C
LOAD
= 10 pF
t
ZX
C
LOAD
= 10 pF
t
INSUPLL
t
INHPLL
t
OUTCOPLL
C
LOAD
= 10 pF
t
XZPLL
C
LOAD
= 10 pF
t
ZXPLL
C
LOAD
= 10 pF
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