參數(shù)資料
型號(hào)： EP1C6T324C8
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁(yè)數(shù)： 30/94頁(yè)
文件大?。?/td> 1138K
代理商： EP1C6T324C8
30
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Independent Clock Mode
The M4K memory blocks implement independent clock mode for true
dual-port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B registers.
Figure 17
shows an M4K memory block in
independent clock mode.
Figure 17. Independent Clock Mode
Note (1)
Note to
Figure 17
:
(1)
All registers shown have asynchronous clear ports.
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren
, and address. The other clock controls the block’s data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers.
Figures 18
and
19
show the memory block in input/output clock
mode.
6
D
ENA
Q
D
ENA
Q
D
ENA
Q
data
A
[ ]
address
A
[ ]
Memory Block
512 ′ 8
1,024 ′ 4
2,048 ′ 2
4,096 ′ 1
Data In
Address A
Write/Read
Enable
Data Out
Data In
Address B
Write/Read
Enable
Data Out
clken
A
clock
A
D
ENA
Q
wren
A
6 LAB Row Clocks
q
A
[ ]
6
data
B
[ ]
address
B
[ ]
clken
B
clock
B
wren
B
q
B
[ ]
ENA
A
B
ENA
D
Q
D
ENA
Q
byteena
A
[ ]
Byte Enable A
Byte Enable B
byteena
B
[ ]
ENA
D
Q
ENA
D
Q
ENA
D
Q
D
Q
Write
Pulse
Generator
Write
Pulse
Generator
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