參數(shù)資料
型號(hào)： EP1C6T324I6
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁(yè)數(shù)： 46/94頁(yè)
文件大?。?/td> 1138K
代理商： EP1C6T324I6
46
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 28. Row I/O Block Connection to the Interconnect
Notes to
Figure 28
:
(1)
The 21 data and control signals consist of three data out lines,
io_dataout[2..0]
, three output enables,
io_coe[2..0]
, three input clock enables,
io_cce_in[2..0]
, three output clock enables,
io_cce_out[2..0]
,
three clocks,
io_cclk[2..0]
, three asynchronous clear signals,
io_caclr[2..0]
, and three synchronous clear
signals,
io_csclr[2..0]
.
(2)
Each of the three IOEs in the row I/O block can have one
io_datain
input (combinatorial or registered) and one
comb_io_datain
(combinatorial) input.
21
R4 Interconnects
C4 Interconnects
I/O Block Local
Interconnect
21 Data and
Control Signals
from Logic Array (1)
io_datain[2..0] and
comb_io_datain[2..0]
(2)
io_clk[5:0]
Row I/O Block
Contains up to
Three IOEs
Direct Link
Interconnect
to Adjacent LAB
Direct Link
Interconnect
from Adjacent LAB
LAB Local
Interconnect
LAB
Row
I/O Block
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