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參數(shù)資料
| 型號(hào)： | EP1K100 |
| 廠商： | Altera Corporation |
| 英文描述： | ACEX 1K Programmable Logic Family(ACEX 1K 系列可編程邏輯) |
| 中文描述： | ACEX一千可編程邏輯系列（ACEX每1000系列可編程邏輯） |
| 文件頁數(shù)： | 39/84頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | EP1K100 |
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Altera Corporation
39
Preliminary Information
ACEX 1K Programmable Logic Family Data Sheet
D
13
T
Notes to tables:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this
frequency. The
f
parameter specifies how much the incoming clock can differ from the specified frequency
during device operation. Simulation does not reflect this parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5
%
of input clock period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the
t
value is less than the time required for configuration.
(4)
The
t
JITTER
specification is measured under long-term observation. The maximum value for
t
JITTER
is 200 ps if
t
INCLKSTB
is lower than 50 ps.
I/O
Configuration
ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via MAX+PLUS II
logic options. The MultiVolt I/O interface is controlled by connecting
V
CCIO
to a different voltage than V
CCINT
. Its effect can be simulated in the
MAX+PLUS II software via the
Global Project Device Options
dialog
box (Assign menu).
This section discusses the PCI pull-up clamping diode option, slew-rate
control, open-drain output option, and MultiVolt I/O interface for
Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
Condition
Min
Typ
Max
Unit
t
R
t
F
t
INDUTY
f
CLK1
Input rise time
Input fall time
Input duty cycle
Input clock frequency (ClockBoost clock
multiplication factor equals 1)
Input clock frequency (ClockBoost clock
multiplication factor equals 2)
Input deviation from user specification in
the MAX+PLUS II software (ClockBoost
clock multiplication factor equals 1)
(1)
t
INCLKSTB
Input clock stability (measured between
adjacent clocks)
t
LOCK
Time required for ClockLock or ClockBoost
to acquire lock
(3)
t
JITTER
Jitter on ClockLock or ClockBoost-
generated clock
(4)
5
5
ns
ns
%
MHz
40
25
60
75
f
CLK2
16
37.5
MHz
f
CLKDEV
25,000
PPM
100
ps
10
μs
t
INCLKSTB
< 100
t
INCLKSTB
< 50
250
(4)
200
(4)
60
ps
ps
%
t
OUTDUTY
Duty cycle for ClockLock or ClockBoost-
generated clock
40
50
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K100FC256-1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-1N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-2N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC2563 | 制造商:Altera Corporation 功能描述: |
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