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參數(shù)資料
| 型號(hào)： | EP1K100 |
| 廠商： | Altera Corporation |
| 英文描述： | ACEX 1K Programmable Logic Family(ACEX 1K 系列可編程邏輯) |
| 中文描述： | ACEX一千可編程邏輯系列（ACEX每1000系列可編程邏輯） |
| 文件頁數(shù)： | 41/84頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | EP1K100 |
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Altera Corporation
41
Preliminary Information
ACEX 1K Programmable Logic Family Data Sheet
D
13
T
The
VCCINT
pins must always be connected to a 2.5-V power supply. With
a 2.5-V V
CCINT
level, input voltages are compatible with 2.5-V, 3.3-V, and
5.0-V inputs. The
VCCIO
pins can be connected to either a 2.5-V or 3.3-V
power supply, depending on the output requirements. When the
VCCIO
pins are connected to a 2.5-V power supply, the output levels are
compatible with 2.5-V systems. When the
VCCIO
pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Devices operating with V
CCIO
levels higher
than 3.0 V achieve a faster timing delay of
t
OD2
instead of
t
OD1
.
Table 13
summarizes ACEX 1K MultiVolt I/O support.
Notes:
(1)
The PCI clamping diode must be disabled to drive an input with voltages higher
than V
CCIO
has.
When V
= 3.3 V, an ACEX 1K device can drive a 2.5-V device that has 3.3-V
tolerant inputs.
(2)
Open-drain output pins on ACEX 1K devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a V
IH
of
3.5 V. When the open-drain pin is active, it will drive low. When the pin
is inactive, the resistor will pull up the trace to 5.0 V. The open-drain pin
will only drive low or tri-state; it will never drive high. The rise time is
dependent on the value of the pull-up resistor and load impedance. The
I
OL
current specification should be considered when selecting a pull-up
resistor.
Power
Sequencing &
Hot-Socketing
Because ACEX 1K devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The V
CCIO
and V
CCINT
power planes can be powered in any
order.
Signals can be driven into ACEX 1K devices before and during power up
without damaging the device. Additionally, ACEX 1K devices do not
drive out during power up. Once operating conditions are reached,
ACEX 1K devices operate as specified by the user.
Table 13. ACEX 1K MultiVolt I/O Support
V
CCIO
(V)
Input Signal (V)
Output Signal (V)
2.5
v
v
3.3
v
(1)
v
5.0
v
(1)
v
(1)
2.5
v
v
(2)
3.3
5.0
2.5
3.3
v
v
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K100FC256-1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC2563 | 制造商:Altera Corporation 功能描述: |
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