參數(shù)資料
型號(hào)： EP1K100
廠商： Electronic Theatre Controls, Inc.
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁(yè)數(shù)： 55/86頁(yè)
文件大小： 992K
代理商： EP1K100
Altera Corporation
55
ACEX 1K Programmable Logic Device Family Data Sheet
D
13
T
t
CASC
t
C
t
CO
t
COMB
t
SU
Cascade-in to cascade-out delay
LE register control signal delay
LE register clock-to-output delay
Combinatorial delay
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
LE register hold time for data and enable signals after clock
LE register preset delay
LE register clear delay
Minimum clock high time from clock pin
Minimum clock low time from clock pin
t
H
t
PRE
t
CLR
t
CH
t
CL
Table 23. IOE Timing Microparameters
Note (1)
Symbol
Parameter
Conditions
t
IOD
t
IOC
t
IOCO
t
IOCOMB
t
IOSU
IOE data delay
IOE register control signal delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
IOE register hold time for data and enable signals after clock
IOE register clear time
Output buffer and pad delay, slow slew rate = off, V
CCIO
= 3.3 V
Output buffer and pad delay, slow slew rate = off, V
CCIO
= 2.5 V
Output buffer and pad delay, slow slew rate = on
IOE output buffer disable delay
IOE output buffer enable delay, slow slew rate = off, V
CCIO
= 3.3 V
IOE output buffer enable delay, slow slew rate = off, V
CCIO
= 2.5 V
IOE output buffer enable delay, slow slew rate = on
IOE input pad and buffer to IOE register delay
IOE register feedback delay
IOE input pad and buffer to FastTrack Interconnect delay
t
IOH
t
IOCLR
t
OD1
t
OD2
t
OD3
t
XZ
t
ZX1
t
ZX2
t
ZX3
t
INREG
t
IOFD
t
INCOMB
C1 = 35 pF
(2)
C1 = 35 pF
(3)
C1 = 35 pF
(4)
C1 = 35 pF
(2)
C1 = 35 pF
(3)
C1 = 35 pF
(4)
Table 22. LE Timing Microparameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K100FC256-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-1N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC2563 制造商:Altera Corporation 功能描述:
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