參數(shù)資料
型號： EP1K10
廠商： Altera Corporation
英文描述： ACEX 1K Programmable Logic Family(ACEX 1K 系列可編程邏輯)
中文描述： ACEX一千可編程邏輯系列（ACEX每1000系列可編程邏輯）
文件頁數(shù)： 32/84頁
文件大?。?/td> 1366K
代理商： EP1K10
32
Altera Corporation
ACEX 1K Programmable Logic Family Data Sheet
Preliminary Information
When dedicated inputs drive non-inverted and inverted peripheral
clears, clock enables, and output enables, two signals on the peripheral
control bus will be used.
Table 7
lists the sources for each peripheral control signal and shows how
the output enable, clock enable, clock, and clear signals share
12 peripheral control signals.
Table 7
also shows the rows that can drive
global signals.
Signals on the peripheral control bus can also drive the four global signals,
referred to as
GLOBAL0
through
GLOBAL3
. An internally generated signal
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives the global signal. This feature is ideal for internally generated clear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routing data signals.
The chip-wide output enable pin is an active-low pin that can be used to
tri-state all pins on the device. This option can be set in the
MAX+PLUS II software. The built-in I/O pin pull-up resistors (which are
active during configuration) are active when the chip-wide output enable
pin is asserted. The registers in the IOE can also be reset by the chip-wide
reset pin.
Table 7. Peripheral Bus Sources for ACEX Devices
Peripheral Control Signal
EP1K10
EP1K30
EP1K50
EP1K100
OE0
Row A
Row A
Row B
Row B
Row C
Row C
Row A
Row A
Row B
Row B
Row C
Row C
Row A
Row B
Row C
Row D
Row E
Row F
Row A
Row B
Row C
Row D
Row E
Row F
Row A
Row B
Row D
Row F
Row H
Row J
Row A
Row C
Row E
Row G
Row I
Row J
Row A
Row C
Row E
Row L
Row I
Row K
Row F
Row D
Row B
Row H
Row J
Row G
OE1
OE2
OE3
OE4
OE5
CLKENA0
/
CLK0
/
GLOBAL0
CLKENA1
/
OE6
/
GLOBAL1
CLKENA2
/
CLR0
CLKENA3
/
OE7
/
GLOBAL2
CLKENA4
/
CLR1
CLKENA5
/
CLK1
/
GLOBAL3
相關(guān)PDF資料
PDF描述
EP1K30 ACEX 1K Programmable Logic Family(ACEX 1K 系列可編程邏輯)
EP1K50 ACEX 1K Programmable Logic Family(ACEX 1K 系列可編程邏輯)
EP1K30TI144-2 Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN
EP1K10 Programmable Logic Device Family
EP1K100 Programmable Logic Device Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Logic Device Family
EP1K100FC256-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*