參數(shù)資料
型號(hào)： EP1K10
廠商： Altera Corporation
英文描述： ACEX 1K Programmable Logic Family(ACEX 1K 系列可編程邏輯)
中文描述： ACEX一千可編程邏輯系列（ACEX每1000系列可編程邏輯）
文件頁(yè)數(shù)： 54/84頁(yè)
文件大?。?/td> 1366K
代理商： EP1K10
54
Altera Corporation
ACEX 1K Programmable Logic Family Data Sheet
Preliminary Information
Table 23. IOE Timing Microparameters
Note (1)
Symbol
Parameter
Conditions
t
IOD
t
IOC
t
IOCO
t
IOCOMB
t
IOSU
IOE data delay
IOE register control signal delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
IOE register hold time for data and enable signals after clock
IOE register clear time
Output buffer and pad delay, slow slew rate = off, V
CCIO
= V
CCINT
Output buffer and pad delay, slow slew rate = off, V
CCIO
= low voltage
Output buffer and pad delay, slow slew rate = on
IOE output buffer disable delay
IOE output buffer enable delay, slow slew rate = off, V
CCIO
= V
CCINT
IOE output buffer enable delay, slow slew rate = off, V
CCIO
= low voltage
IOE output buffer enable delay, slow slew rate = on
IOE input pad and buffer to IOE register delay
IOE register feedback delay
IOE input pad and buffer to FastTrack Interconnect delay
t
IOH
t
IOCLR
t
OD1
t
OD2
t
OD3
t
XZ
t
ZX1
t
ZX2
t
ZX3
t
INREG
t
IOFD
t
INCOMB
C1 = 35 pF
(2)
C1 = 35 pF
(3)
C1 = 35 pF
(4)
C1 = 35 pF
(2)
C1 = 35 pF
(3)
C1 = 35 pF
(4)
Table 24. EAB Timing Microparameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
t
EABDATA1
t
EABDATA2
t
EABWE1
t
EABWE2
t
EABRE1
t
EABRE2
t
EABCLK
t
EABCO
t
EABBYPASS
t
EABSU
t
EABH
t
EABCLR
t
EABCH
t
EABCL
t
AA
Data or address delay to EAB for combinatorial input
Data or address delay to EAB for registered input
Write enable delay to EAB for combinatorial input
Write enable delay to EAB for registered input
Read enable delay to EAB for combinatorial input
Read enable delay to EAB for registered input
EAB register clock delay
EAB register clock-to-output delay
Bypass register delay
EAB register setup time before clock
EAB register hold time after clock
EAB register asynchronous clear time to output delay
Clock high time
Clock low time
Address access delay (including the read enable to output delay)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K100 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Programmable Logic Device Family
EP1K100FC256-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-1N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FC256-2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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