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參數(shù)資料
| 型號： | EP1K30TI144-2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN |
| 中文描述： | 可編程邏輯器件（992.51十一） |
| 文件頁數(shù)： | 58/86頁 |
| 文件大小： | 992K |
| 代理商： | EP1K30TI144-2 |
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58
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
(2)
Operating conditions: V
CCIO
= 3.3 V ± 10
%
for commercial or industrial use in ACEX 1K devices
(3)
Operating conditions: V
CCIO
= 2.5 V ± 5
%
for commercial or industrial use in ACEX 1K devices.
(4)
Operating conditions: V
CCIO
= 2.5 V or 3.3 V.
(5)
Because the RAM in the EAB is self-timed, this parameter can be ignored when the
WE
signal is registered.
(6)
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
(7)
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
Table 26. Interconnect Timing Microparameters
Note (1)
Symbol
Parameter
Conditions
t
DIN2IOE
t
DIN2LE
t
DIN2DATA
t
DCLK2IOE
t
DCLK2LE
t
SAMELAB
t
SAMEROW
Delay from dedicated input pin to IOE control input
Delay from dedicated input pin to LE or EAB control input
Delay from dedicated input or clock to LE or EAB data
Delay from dedicated clock pin to IOE clock
Delay from dedicated clock pin to LE or EAB clock
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
Routing delay for an LE driving an IOE in the same column
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
(7)
(7)
(7)
(7)
(7)
(7)
(7)
t
SAMECOLUMN
t
DIFFROW
(7)
(7)
t
TWOROWS
t
LEPERIPH
(7)
(7)
t
LABCARRY
t
LABCASC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K30TI144-2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 216 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Logic Device Family |
| EP1K50FC256-1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K50FC256-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC256-1F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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