參數(shù)資料
型號(hào): EP20K1000E
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁數(shù): 43/117頁
文件大?。?/td> 570K
代理商: EP20K1000E
Altera Corporation
43
APEX 20K Programmable Logic Device Family Data Sheet
Figure 28
shows how a column IOE connects to the interconnect.
Figure 28. Column IOE Connection to the Interconnect
Dedicated Fast I/O Pins
APEX 20KE devices incorporate an enhancement to support bidirectional
pins with high internal fanout such as PCI control signals. These pins are
called Dedicated Fast I/O pins (
FAST1
,
FAST2
,
FAST3
, and
FAST4
) and
replace dedicated inputs. These pins can be used for fast clock, clear, or
high fanout logic signal distribution. They also can drive out. The
Dedicated Fast I/O pin data output and tri-state control are driven by
local interconnect from the adjacent MegaLAB for high speed.
Row In
terc
onn
ect
Column In
terc
onn
ect
E
ac
h IOE
ca
n
dr
iv
e
c
olumn in
terc
onn
ect
. In APEX
2
0KE
de
vi
ces
,
IOE
s
ca
n
a
l
s
o
dr
iv
e
F
ast
Row in
terc
onn
ect
. E
ac
h IOE
data
a
n
d
OE
s
ign
a
l i
s
dr
iv
e
n by lo
ca
l in
terc
onn
ect
.
Any LE o
r
ESB
ca
n
dr
iv
e
a
c
olumn pin
t
h
r
ough
a
r
ow,
c
olumn,
a
n
d
M
e
g
a
LAB
in
terc
onn
ect
.
IOE
IOE
LAB
An LE o
r
ESB
ca
n
dr
iv
e
a
pin
t
h
r
ough
a
lo
ca
l
in
terc
onn
ect
fo
r
f
aster
c
lo
c
k-
t
o-ou
t
pu
t
t
im
es
.
M
e
g
a
LAB In
terc
onn
ect
相關(guān)PDF資料
PDF描述
EP20K100E Programmable Logic Device Family
EP20K1500E Programmable Logic Device Family
EP20K160E Programmable Logic Device Family
EP20K200 Programmable Logic Device Family
EP20K200E Programmable Logic Device Family
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EP20K1000EBC652-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EBC652-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K1000EBC652-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EBC652-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EBC652-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA